Cortex-R Port Improvement for 2.2

arch/Kconfig

@@ -422,6 +422,12 @@ config CPU_HAS_TEE
 	  Execution Environment (e.g. when it has a security attribution
 	  unit).
 
+config CPU_HAS_DCLS
+	bool
+	help
+	  This option is enabled when the processor hardware is configured in
+	  Dual-redundant Core Lock-step (DCLS) topology.
+
 config CPU_HAS_FPU
 	bool
 	help

arch/arm/core/CMakeLists.txt

@@ -10,7 +10,7 @@ zephyr_library_sources(
   exc_exit.S
   swap.c
   swap_helper.S
-  irq_manage.c
+  irq.c
   thread.c
   cpu_idle.S
   fault_s.S

arch/arm/core/Kconfig

@@ -31,6 +31,7 @@ config CPU_CORTEX_M
 config CPU_CORTEX_R
 	bool
 	select CPU_CORTEX
+	select HAS_CMSIS_CORE
 	select HAS_FLASH_LOAD_OFFSET
 	help
 	  This option signifies the use of a CPU of the Cortex-R family.
@@ -76,9 +77,24 @@ config ISA_ARM
 	  processor start-up. Much of its functionality was subsumed into T32 with
 	  the introduction of Thumb-2 technology.
 
+config COMPILER_ISA_THUMB2
+	bool "Compile C functions using Thumb-2 instruction set"
+	depends on ISA_THUMB2
+	default y
+	help
+	  This option configures the compiler to compile all C functions using the
+	  Thumb-2 instruction set.
+
 config NUM_IRQS
 	int
 
+config IRQ_COMMON_EOI
+	bool
+	help
+	  This option signifies that the architectural interrupt controller
+	  requires a common End of Interrupt (EOI) action after servicing every
+	  interrupt.
+
 config STACK_ALIGN_DOUBLE_WORD
 	bool "Align stacks on double-words (8 octets)"
 	default y
@@ -98,6 +114,12 @@ config RUNTIME_NMI
 	  NMI handler installed when the CPU boots. If a custom handler is
 	  needed, enable this option and attach it via _NmiHandlerSet().
 
+config PLATFORM_SPECIFIC_INIT
+	bool "Enable platform (SOC) specific startup hook"
+	help
+	  The platform specific initialization code (z_platform_init) is executed
+	  at the beginning of the startup code (__start).
+
 config FAULT_DUMP
 	int "Fault dump level"
 	default 2

arch/arm/core/cortex_m/CMakeLists.txt

@@ -8,6 +8,7 @@ zephyr_library_sources(
   fault.c
   scb.c
   irq_init.c
+  irq_manage.c
   thread_abort.c
   )
 

arch/arm/core/cortex_m/Kconfig

@@ -258,12 +258,6 @@ config SW_VECTOR_RELAY
 	  (or an Armv8-M baseline core) with no VTOR and no other hardware
 	  relocation table mechanisms.
 
-config PLATFORM_SPECIFIC_INIT
-	bool "Enable platform (SOC) specific startup hook"
-	help
-	  The platform specific initialization code (z_platform_init) is executed
-	  at the beginning of the startup code (__start).
-
 endmenu
 
 endif # CPU_CORTEX_M

arch/arm/core/irq_manage.c → arch/arm/core/cortex_m/irq_manage.c

@@ -6,7 +6,7 @@
 
 /**
  * @file
- * @brief ARM Cortex-M and Cortex-R interrupt management
+ * @brief ARM Cortex-M interrupt management
  *
  *
  * Interrupt management: enabling/disabling and dynamic ISR
@@ -16,12 +16,7 @@
 
 #include <kernel.h>
 #include <arch/cpu.h>
-#if defined(CONFIG_CPU_CORTEX_M)
 #include <arch/arm/cortex_m/cmsis.h>
-#elif defined(CONFIG_CPU_CORTEX_R)
-#include <device.h>
-#include <irq_nextlevel.h>
-#endif
 #include <sys/__assert.h>
 #include <toolchain.h>
 #include <linker/sections.h>
@@ -32,7 +27,6 @@
 
 extern void z_arm_reserved(void);
 
-#if defined(CONFIG_CPU_CORTEX_M)
 #define NUM_IRQS_PER_REG 32
 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
@@ -97,121 +91,6 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
 
-#elif defined(CONFIG_CPU_CORTEX_R)
-void z_arch_irq_enable(unsigned int irq)
-{
-	struct device *dev = _sw_isr_table[0].arg;
-
-	irq_enable_next_level(dev, (irq >> 8) - 1);
-}
-
-void z_arch_irq_disable(unsigned int irq)
-{
-	struct device *dev = _sw_isr_table[0].arg;
-
-	irq_disable_next_level(dev, (irq >> 8) - 1);
-}
-
-int z_arch_irq_is_enabled(unsigned int irq)
-{
-	struct device *dev = _sw_isr_table[0].arg;
-
-	return irq_is_enabled_next_level(dev);
-}
-
-/**
- * @internal
- *
- * @brief Set an interrupt's priority
- *
- * The priority is verified if ASSERT_ON is enabled. The maximum number
- * of priority levels is a little complex, as there are some hardware
- * priority levels which are reserved: three for various types of exceptions,
- * and possibly one additional to support zero latency interrupts.
- *
- * @return N/A
- */
-void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
-{
-	struct device *dev = _sw_isr_table[0].arg;
-
-	if (irq == 0)
-		return;
-
-	irq_set_priority_next_level(dev, (irq >> 8) - 1, prio, flags);
-}
-
-#endif
-
-/**
- *
- * @brief Spurious interrupt handler
- *
- * Installed in all dynamic interrupt slots at boot time. Throws an error if
- * called.
- *
- * See z_arm_reserved().
- *
- * @return N/A
- */
-void z_irq_spurious(void *unused)
-{
-	ARG_UNUSED(unused);
-	z_arm_reserved();
-}
-
-/* FIXME: IRQ direct inline functions have to be placed here and not in
- * arch/cpu.h as inline functions due to nasty circular dependency between
- * arch/cpu.h and kernel_structs.h; the inline functions typically need to
- * perform operations on _kernel.  For now, leave as regular functions, a
- * future iteration will resolve this.
- *
- * See https://github.com/zephyrproject-rtos/zephyr/issues/3056
- */
-
-#ifdef CONFIG_SYS_POWER_MANAGEMENT
-void _arch_isr_direct_pm(void)
-{
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
-	|| defined(CONFIG_ARMV7_R)
-	unsigned int key;
-
-	/* irq_lock() does what we wan for this CPU */
-	key = irq_lock();
-#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	/* Lock all interrupts. irq_lock() will on this CPU only disable those
-	 * lower than BASEPRI, which is not what we want. See comments in
-	 * arch/arm/core/isr_wrapper.S
-	 */
-	__asm__ volatile("cpsid i" : : : "memory");
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-
-	if (_kernel.idle) {
-		s32_t idle_val = _kernel.idle;
-
-		_kernel.idle = 0;
-		z_sys_power_save_idle_exit(idle_val);
-	}
-
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
-	|| defined(CONFIG_ARMV7_R)
-	irq_unlock(key);
-#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile("cpsie i" : : : "memory");
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-
-}
-#endif
-
-void z_arch_isr_direct_header(void)
-{
-	sys_trace_isr_enter();
-}
-
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
 /**
  *
@@ -267,14 +146,3 @@ int irq_target_state_is_secure(unsigned int irq)
 }
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
-
-#ifdef CONFIG_DYNAMIC_INTERRUPTS
-int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			      void (*routine)(void *parameter), void *parameter,
-			      u32_t flags)
-{
-	z_isr_install(irq, routine, parameter);
-	z_arm_irq_priority_set(irq, priority, flags);
-	return irq;
-}
-#endif /* CONFIG_DYNAMIC_INTERRUPTS */

arch/arm/core/cortex_r/CMakeLists.txt

@@ -6,6 +6,7 @@ zephyr_library_sources(
   vector_table.S
   reset.S
   fault.c
+  irq_init.c
   reboot.c
   stacks.c
   )

arch/arm/core/cortex_r/Kconfig

@@ -36,6 +36,7 @@ config ARMV7_R
 	bool
 	select ATOMIC_OPERATIONS_BUILTIN
 	select ISA_ARM
+	select ISA_THUMB2
 	help
 	  This option signifies the use of an ARMv7-R processor
 	  implementation.
@@ -78,17 +79,19 @@ config ARMV7_SYS_STACK_SIZE
 	help
 	  This option specifies the size of the stack used by the system mode.
 
-if CPU_CORTEX_R
-
 config RUNTIME_NMI
 	default y
 
 config GEN_ISR_TABLES
 	default y
 
-config GEN_IRQ_VECTOR_TABLE
-	default n
-
-endif # CPU_CORTEX_R
+config VIC_IRQ_VECTOR
+	bool "Enable VIC port hardware IRQ vector"
+	depends on (CPU_CORTEX_R4 || CPU_CORTEX_R5)
+	help
+	  Enable hardware IRQ vector using the handler address provided by the
+	  the system interrupt controller through VIC port. When this option is
+	  selected, the IRQ vector (offset 0x18) in the CPU exception vector table
+	  is not used.
 
 endif # CPU_CORTEX_R

arch/arm/core/cortex_r/irq_init.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief ARM Cortex-R interrupt initialization
+ */
+
+#include <arch/cpu.h>
+#include <arch/arm/cortex_r/cmsis.h>
+
+/**
+ * @brief Initialize interrupts
+ *
+ * @return N/A
+ */
+
+void z_arm_int_lib_init(void)
+{
+    /* Invoke SoC-specific interrupt initialisation */
+    z_soc_irq_init();
+
+    /* Configure hardware vectored interrupt mode.*/
+#if defined(CONFIG_VIC_IRQ_VECTOR)
+    unsigned int sctlr = __get_SCTLR();
+    sctlr |= SCTLR_VE_Msk;
+    __set_SCTLR(sctlr);
+#endif
+}