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drivers: dma: intel_adsp_hda: Fix L1 exit condition #69480
drivers: dma: intel_adsp_hda: Fix L1 exit condition #69480
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Please submit this to SOF CI using a draft PR. Like this: thesofproject/sof#8819 |
DO NOT MERGE! CI RUN ONLY. Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
@marc-hb this has also been tested (in a slightly different but verifiably equivalent form) by thesofproject/sof#8732 |
It seems like we've had a number of patches in this area now and none of them were entirely sufficient. It would really be great to see a test case covering this stuff to build some confidence and avoid regressions. |
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Approving, but truly a test case covering this L1 exit path would be greatly appreciated. This must be the 3rd or 4th patch I've seen around this area.
BTW I asked in #66042 (comment) why MTL and LNL are configured differently but I didn't see an answer. |
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Needs converting to hwmv2
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I had to drop this patch from #69547 to make Chain DMA and probe quickbuild tests pass. With this commit in the set I was getting zero buffer size readings from the controller, which led to easily reproducible test failures
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DO NOT MERGE! CI RUN ONLY. Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
*** DO NOT MERGE! CI RUN ONLY! *** Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
*** DO NOT MERGE! CI RUN ONLY! *** Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
*** DO NOT MERGE! CI RUN ONLY! *** Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
*** DO NOT MERGE! CI RUN ONLY! *** Tests "Fix L1 exit condiotion" Zephyr PR zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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Transition to a low power DMI L1 state should be allowed only after all pending DMA channels transfers have started. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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@nordicjm , PR was rebased to main, so no problem with hwmv2 now. Could you guys approve/remove "change request" ? |
*** DO NOT MERGE *** *** CI RUN ONLY *** CI run for Zephyr L1 EXIT workaround zephyrproject-rtos/zephyr#69480 Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
thesofproject/sof#8947 passed QB testing with this PR
Transition to a low power DMI L1 state should be allowed only after all pending DMA channels transfers have started.