Single netlist mode

.github/workflows/regression.yml

@@ -31,7 +31,8 @@ jobs:
 
       - name: Run pytest
         working-directory: examples
-        run: pytest --durations=0 -s
+        run: |
+          pytest --durations=0 -s
 
       - name: Run tests
         working-directory: tests

examples/clean.sh

@@ -0,0 +1,12 @@
+#!/bin/bash
+
+# Loop through subdirectories, running 'make clean'
+
+for dir in */; do
+    # Run 'make clean' if a Makefile exists
+
+    if [ -f "${dir}Makefile" ]; then
+        echo "Running 'make clean' in $dir"
+        (cd "$dir" && make clean)
+    fi
+done

examples/network-fifo-chain/Makefile

@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+.PHONY: verilator
+verilator:
+	./test.py --tool verilator --start-delay 5 --max-rate 1e3
+
+.PHONY: verilator-single-netlist
+verilator-single-netlist:
+	./test.py --tool verilator --single-netlist
+
+.PHONY: icarus
+icarus:
+	./test.py --tool icarus --start-delay 2 --max-rate 1e3 --fifos 125
+
+.PHONY: icarus-single-netlist
+icarus-single-netlist:
+	./test.py --tool icarus --single-netlist
+
+.PHONY: clean
+clean:
+	rm -f queue-* *.q
+	rm -f *.vcd *.fst *.fst.hier
+	rm -rf obj_dir build
+	rm -f *.o *.vpi

examples/network-fifo-chain/test.py

@@ -0,0 +1,130 @@
+#!/usr/bin/env python3
+
+# Example showing how to wire up various modules using SbNetwork
+
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+import umi
+from switchboard import SbNetwork, umi_loopback
+from switchboard.cmdline import get_cmdline_args
+
+from pathlib import Path
+THIS_DIR = Path(__file__).resolve().parent
+
+
+def main():
+    # create network
+
+    extra_args = {
+        '--packets': dict(type=int, default=1000, help='Number of'
+        ' transactions to send into the FIFO during the test.'),
+        '--fifos': dict(type=int, default=500, help='Number of'
+        ' FIFOs to instantiate in series for this test.'),
+        '--fifos-per-sim': dict(type=int, default=1, help='Number of'
+        ' FIFOs to include in each simulation.')
+    }
+
+    # workaround - need to see what type of simulation we're running
+    # (network of simulations, network of networks, single netlist)
+
+    args = get_cmdline_args(extra_args=extra_args)
+
+    assert args.fifos % args.fifos_per_sim == 0, \
+        'Number of FIFOs must be divisible by the number of FIFOs per simulation'
+
+    if args.fifos_per_sim in [1, args.fifos]:
+        # single network
+        net = SbNetwork(cmdline=True, single_netlist=args.fifos_per_sim == args.fifos)
+        subnet = net
+        n = args.fifos
+    else:
+        # network of networks
+        net = SbNetwork(cmdline=True, single_netlist=False)
+        subnet = SbNetwork(name='subnet', cmdline=True, single_netlist=True)
+        n = args.fifos_per_sim
+
+    subblock = make_umi_fifo(subnet)
+
+    subblocks = [subnet.instantiate(subblock) for _ in range(n)]
+
+    for i in range(len(subblocks) - 1):
+        subnet.connect(subblocks[i].umi_out, subblocks[i + 1].umi_in)
+
+    if n < args.fifos:
+        subnet.external(subblocks[0].umi_in, name='umi_in')
+        subnet.external(subblocks[-1].umi_out, name='umi_out')
+
+        blocks = [net.instantiate(subnet) for _ in range(args.fifos // args.fifos_per_sim)]
+
+        for i in range(len(blocks) - 1):
+            net.connect(blocks[i].umi_out, blocks[i + 1].umi_in)
+    else:
+        blocks = subblocks
+
+    net.external(blocks[0].umi_in, txrx='umi')
+    net.external(blocks[-1].umi_out, txrx='umi')
+
+    # build simulator
+
+    net.build()
+
+    # launch the simulation
+
+    net.simulate()
+
+    # interact with the simulation
+
+    umi_loopback(net.intfs['umi'], packets=args.packets)
+
+
+def make_umi_fifo(net):
+    dw = 256
+    aw = 64
+    cw = 32
+
+    parameters = dict(
+        DW=dw,
+        AW=aw,
+        CW=cw
+    )
+
+    tieoffs = dict(
+        bypass="1'b0",
+        chaosmode="1'b0",
+        fifo_full=None,
+        fifo_empty=None,
+        vdd="1'b1",
+        vss="1'b0"
+    )
+
+    interfaces = {
+        'umi_in': dict(type='umi', dw=dw, aw=aw, cw=cw, direction='input'),
+        'umi_out': dict(type='umi', dw=dw, aw=aw, cw=cw, direction='output')
+    }
+
+    clocks = [
+        'umi_in_clk',
+        'umi_out_clk'
+    ]
+
+    resets = [
+        'umi_in_nreset',
+        'umi_out_nreset'
+    ]
+
+    dut = net.make_dut('umi_fifo', parameters=parameters, interfaces=interfaces,
+        clocks=clocks, resets=resets, tieoffs=tieoffs)
+
+    dut.use(umi)
+    dut.add('option', 'library', 'umi')
+    dut.add('option', 'library', 'lambdalib_stdlib')
+    dut.add('option', 'library', 'lambdalib_ramlib')
+
+    dut.input('umi/rtl/umi_fifo.v', package='umi')
+
+    return dut
+
+
+if __name__ == '__main__':
+    main()

examples/network/Makefile

@@ -5,10 +5,18 @@
 verilator:
 	./test.py --tool verilator --start-delay 1 --max-rate 1e3
 
+.PHONY: verilator-single-netlist
+verilator-single-netlist:
+	./test.py --tool verilator --single-netlist
+
 .PHONY: icarus
 icarus:
 	./test.py --tool icarus --start-delay 1 --max-rate 1e3
 
+.PHONY: icarus-single-netlist
+icarus-single-netlist:
+	./test.py --tool icarus --single-netlist
+
 .PHONY: clean
 clean:
 	rm -f queue-* *.q

examples/network/test.py

@@ -8,7 +8,7 @@
 import numpy as np
 
 import umi
-from switchboard import SbDut, SbNetwork
+from switchboard import SbNetwork
 
 from pathlib import Path
 THIS_DIR = Path(__file__).resolve().parent
@@ -21,9 +21,9 @@ def main():
 
     # create the building blocks
 
-    umi_fifo = make_umi_fifo(args=net.args)
-    umi2axil = make_umi2axil(args=net.args)
-    axil_ram = make_axil_ram(args=net.args)
+    umi_fifo = make_umi_fifo(net)
+    umi2axil = make_umi2axil(net)
+    axil_ram = make_axil_ram(net)
 
     # connect them together
 
@@ -68,7 +68,7 @@ def main():
     assert wrdata == rddata
 
 
-def make_umi_fifo(args):
+def make_umi_fifo(net):
     dw = 256
     aw = 64
     cw = 32
@@ -103,18 +103,20 @@ def make_umi_fifo(args):
         'umi_out_nreset'
     ]
 
-    dut = SbDut('umi_fifo', autowrap=True, parameters=parameters, interfaces=interfaces,
-        clocks=clocks, resets=resets, tieoffs=tieoffs, args=args)
+    dut = net.make_dut('umi_fifo', parameters=parameters, interfaces=interfaces,
+        clocks=clocks, resets=resets, tieoffs=tieoffs)
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
     dut.add('option', 'library', 'lambdalib_stdlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
+    dut.input('umi/rtl/umi_fifo.v', package='umi')
+
     return dut
 
 
-def make_axil_ram(args):
+def make_axil_ram(net):
     dw = 64
     aw = 13
 
@@ -129,8 +131,8 @@ def make_axil_ram(args):
 
     resets = [dict(name='rst', delay=8)]
 
-    dut = SbDut('axil_ram', autowrap=True, parameters=parameters, interfaces=interfaces,
-        resets=resets, args=args)
+    dut = net.make_dut('axil_ram', parameters=parameters,
+        interfaces=interfaces, resets=resets)
 
     dut.register_package_source(
         'verilog-axi',
@@ -146,7 +148,7 @@ def make_axil_ram(args):
     return dut
 
 
-def make_umi2axil(args):
+def make_umi2axil(net):
     dw = 64
     aw = 64
     cw = 32
@@ -165,14 +167,16 @@ def make_umi2axil(args):
 
     resets = ['nreset']
 
-    dut = SbDut('umi2axilite', autowrap=True, parameters=parameters, interfaces=interfaces,
-        resets=resets, args=args)
+    dut = net.make_dut('umi2axilite', parameters=parameters,
+        interfaces=interfaces, resets=resets)
 
     dut.use(umi)
     dut.add('option', 'library', 'umi')
     dut.add('option', 'library', 'lambdalib_stdlib')
     dut.add('option', 'library', 'lambdalib_ramlib')
 
+    dut.input('utils/rtl/umi2axilite.v', package='umi')
+
     return dut
 
 

examples/requirements.txt

@@ -1,2 +1,2 @@
 # Examples dependencies
-umi @ git+https://github.com/zeroasiccorp/umi.git@f6d8fea9e6270b89a2c38860a4af512383cbc6ef
+umi @ git+https://github.com/zeroasiccorp/umi.git@main

examples/test_examples.py

@@ -21,6 +21,8 @@
     ['minimal', 'PASS!', 'verilator'],
     ['network', None, 'verilator'],
     ['network', None, 'icarus'],
+    ['network', None, 'verilator-single-netlist'],
+    ['network', None, 'icarus-single-netlist'],
     ['python', 'PASS!', None],
     ['router', 'PASS!', None],
     ['stream', 'PASS!', None],

setup.py

@@ -6,7 +6,7 @@
 from setuptools import setup, find_packages
 from pybind11.setup_helpers import Pybind11Extension, build_ext
 
-__version__ = "0.2.1"
+__version__ = "0.2.2"
 
 #################################################################################
 # parse_reqs, long_desc from https://github.com/siliconcompiler/siliconcompiler #