GitHub - zig-kwin-hu/jiyuan

Name		Name	Last commit message	Last commit date
Latest commit History 35 Commits
Decode		Decode
AluSrcMUX.vhd		AluSrcMUX.vhd
CPU.vhd		CPU.vhd
DERegister.vhd		DERegister.vhd
EMRegister.vhd		EMRegister.vhd
FDRegister.vhd		FDRegister.vhd
Forward.vhd		Forward.vhd
ForwardMUX.vhd		ForwardMUX.vhd
ID_ADD.vhd		ID_ADD.vhd
ID_JMPControl.vhd		ID_JMPControl.vhd
ID_PCselector.vhd		ID_PCselector.vhd
ID_topmodual.vhd		ID_topmodual.vhd
IFIDRegister.vhd		IFIDRegister.vhd
IO.vhd		IO.vhd
MWRegister.vhd		MWRegister.vhd
PCAdd1.vhd		PCAdd1.vhd
PCMem.vhd		PCMem.vhd
PCRegister.vhd		PCRegister.vhd
PCSim.vhd		PCSim.vhd
PC_topmodual.vhd		PC_topmodual.vhd
PCchoose.vhd		PCchoose.vhd
README.md		README.md
ToRegMux.vhd		ToRegMux.vhd
alu.vhd		alu.vhd
cpu.vhd		cpu.vhd
datahazard.vhd		datahazard.vhd
immediate_expand.vhd		immediate_expand.vhd
reg.vhd		reg.vhd

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4个阶段寄存器存储数据

有一控制信号判断是否保持（暂停）

ALU,Op码对应关系

null 0000
+ 0001
& 0010
- 0011
| 0100
逻辑<< 0101
< 0110
数字>> 0111
逻辑>> 1000
!= 1001

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VHDL 100.0%