Several files use the $clog2 function, which is not supported by Xilinx synthesis (at least 2016.4)

[bchetwynd]

The following is a list when the $clog2 function is used:

bench/formal/faxis_master.v: ? 1 : $clog2(F_MAX_STALL+2);
bench/formal/faxis_slave.v: ? 1 : $clog2(F_MAX_STALL+2);
bench/formal/fwbc_slave.v: localparam DLYBITS= $clog2(F_MAX_DELAY+1);
bench/formal/axi_addr_miter.v: localparam DSZ = $clog2(DW)-3;
bench/formal/fwbc_master.v: localparam DLYBITS= $clog2(F_MAX_DELAY+1);
bench/formal/xlnxstream_2018_3.v: localparam F_LGDEPTH = $clog2(NUMBER_OF_OUTPUT_WORDS+1)+2;
rtl/axilwr2wbsp.v: localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3;
rtl/axilxbar.v: localparam LGLINGER = (OPT_LINGER>1) ? $clog2(OPT_LINGER+1) : 1;
rtl/axilxbar.v: localparam LGNM = (NM>1) ? $clog2(NM) : 1;
rtl/axilxbar.v: localparam LGNS = (NS>1) ? $clog2(NS+1) : 1;
rtl/axilxbar.v: // is $clog2(NS+1) rather than $clog2(NS). The extra bits
rtl/axilxbar.v: // reg [((NS>1)?$clog2(NS)-1:0):0] windex;
rtl/axilite2axi.v: assign M_AXI_AWSIZE = $clog2(C_AXI_DATA_WIDTH)-3;
rtl/axilite2axi.v: assign M_AXI_ARSIZE = $clog2(C_AXI_ADDR_WIDTH)-3;
rtl/axi_addr.v: localparam DSZ = $clog2(DW)-3;
rtl/axilrd2wbsp.v: localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3;
rtl/axi2axilite.v: localparam LSB = $clog2(C_AXI_DATA_WIDTH)-3;
rtl/axisafety.v: localparam LGTIMEOUT = $clog2(OPT_TIMEOUT+1);
rtl/axisafety.v: localparam LSB = $clog2(DW)-3;
rtl/wbm2axisp.v: localparam LG_AXI_DW = $clog2(C_AXI_DATA_WIDTH);
rtl/wbm2axisp.v: localparam LG_WB_DW = $clog2(DW);
rtl/wbm2axisp.v: localparam DWSIZE = $clog2(DW)-3;
rtl/wbm2axisp.v: // wire [(C_AXI_DATA_WIDTH>DW ? $clog2(C_AXI_DATA_WIDTH/DW):0)+$clog2(DW)-4:0] axi_lsbs;
rtl/wbm2axisp.v: wire [$clog2(DW)-4:0] axi_lsbs;
rtl/wbm2axisp.v: // wire [$clog2(DW)-4:0] axi_lsbs;
rtl/wbm2axisp.v: assume(f_const_addr[$clog2(DW)-4:0] == 0);
rtl/axixbar.v: localparam LGLINGER = (OPT_LINGER>1) ? $clog2(OPT_LINGER+1) : 1;
rtl/axixbar.v: localparam LGNM = (NM>1) ? $clog2(NM) : 1;
rtl/axixbar.v: localparam LGNS = (NS>1) ? $clog2(NS+1) : 1;
rtl/axixbar.v: // reg [((NM>1)?($clog2(NM)-1):0):0] rindex;
rtl/wbxbar.v: localparam TIMEOUT_WIDTH = $clog2(OPT_TIMEOUT);
rtl/wbxbar.v: localparam LGNM = (NM>1) ? $clog2(NM) : 1;
rtl/wbxbar.v: localparam LGNS = $clog2(NS+1);
rtl/demofull.v: localparam LSB = $clog2(C_S_AXI_DATA_WIDTH)-3;

However, this is not support by Xilinx Vivado Synthesis 2016.4 (I have not tried other versions as I am locked to 2016.4)

Recommend doing something like this to address:

https://stackoverflow.com/questions/5269634/address-width-from-ram-depth

[ZipCPU]

The $clog2 function is supported by Verilator, Yosys, and even Vivado 2018.3--which is the one I'm using.

Feel free to make those changes to a local copy. That seems to make more sense than downgrading the rest of the repository for a tool issue that's fixed in a later release.

Dan