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I am getting error while excuting make in zbasic #10
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Thanks for pointing this out! I see three issues in what you've shared, all things fixed in the dev branch that haven't made it to the master.
The reason dev hasn't been ported to master is simply because ... there's been so many changes. One in particular breaks a lot of interfaces, and I want to make certain the ZipCPU documentation is up to date on that change before I push it. (The one that breaks everything is the ZipCPU's debug interface. That's gone from a two register interface to a 64-register interface. The result is a lot faster to debug over a serial port--it just needs to be documented properly.) Other upgrades include a profiling port, the ability to use buses wider than 32-bits, AXI support, a DMA rewrite, a bit of a shuffling of bit allocations in the debugging interface, and ... more. But I digress. Dan |
These issues should be fixed now in ccc0a4b1. I have tested and verified that the design works using Verilator 4.2. Dan |
Thank you very much, now i can build it without any errors using branch ccc0a4b1. But still some minor warnings are present as mentioned below but otherwise it is OK for now
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I think I just responded to almost all of these while responding to this issue, with the exception of the The issue there is that none of my Verilog files have (or require) a timescale statement in them. Verilog doesn't use assignment delays, so this isn't an issue. At one point, however, Verilator decided to make a warning of this fact, deciding that all Verilog files should have a timescale statement. The Dan |
Thank you very much Dan |
Hi,
i am getting following warnings and error while executing make in zbasic directory, please help me on this.
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