DRAMRouter
This project makes use of 64MBytes DDR2 DRAM on the NetFPGA card for packet buffering. The design has 8 DRAM queues completely replace the SRAM output queues
- Status :
- Version :
- Author :
- NetFPGA source (required only for project source release) :
The DRAM router is released with NetFPGA 2.0 Beta Base.
The regression tests verify the functionality of the dram_router. In order to run the tests, you need to have the machine connected for the regression tests as stated in the Run Regression Tests section of the Guide.
After connecting the cables. Run the following command to run the regression tests.
nf2_regress_test.pl --project dram_router
Most of the regression tests of the project are the same to the reference router. This is by design because we want to demonstrate that the DDR2 DRAM has the same (actually even higher) ability of packet buffering. Follow the Beta Release Regression Tests for details of those tests.
Moreover, the project has some extra tests that verifies the counters of DDR2 DRAM counters. They are described as follows.
- Project :
- Name :
- Description:
- Turn off the shortcut of 8 queues
- Send a number of packets, which go through DDR2 DRAM
- Turn on the shortcut, allowing those words stored in tail cache going out
- Verify the counters: Input words, Output words, Shortcut words, DRAM write words, DRAM read words
- Location
projects/dram_router/regress/test_dram_queue
- Output
SUCCESS!
- Project :
- Name :
- Description:
- Clear the ARP table and the Routing Table
- Set nf2c2 and nf2c3 PHYs in the loopback mode
- Clear all four CPU Output Queues' dropped packet counter and dequeued packet counter
- Set all four CPU Output Queue sizes to 8KB each. Disable CPU Output Queue dequeuing service
- Generate 9 packets for each interface of eth1, eth2, nf2c2, nf2c3. Every packet is of size (1024-8)=1016 bytes. Send these packets out of the interfaces eth1, eth2, nf2c2, nf2c3
- Check each CPU Output Queue stored packet counter is 8 packet and the dropped packet counter is 1
- Then enable all four CPU Output Queue dequeuing service, check each CPU Output Queue dequeued packet counter is 8, and the first 8 packets sent out at eth1, eth2, nf2c2, nf2c3 match the 8 packets which the driver receives from the CPU Output Queues for nf2c0, nf2c1, nf2c2, nf2c3
- Location
projects/dram_router/regress/test_oq_dram_sz_cpu
- Output
SUCCESS!
- Project :
- Name :
- Description:
- Clear the ARP table and the Routing Table
- Set nf2c2 and nf2c3 PHYs in the loopback mode
- Clear all four MAC Output Queues' dropped packet counter and dequeued packet counter
- Set all four MAC Output Queue sizes to 8KB each. Disable CPU Output Queue dequeuing service
- Generate 9 packets for each interface of eth1, eth2, nf2c2, nf2c3. Every packet is of size (1024-8)=1016 bytes. Send these packets out of the interfaces eth1, eth2, nf2c2, nf2c3
- Check each MAC Output Queue stored packet counter is 8 packet and the dropped packet counter is 1
- Then enable all four CPU Output Queue dequeuing service, check each CPU Output Queue dequeued packet counter is 8, and the first 8 packets sent out at eth1, eth2, nf2c2, nf2c3 match the 8 packets which the driver receives from the CPU Output Queues for nf2c0, nf2c1, nf2c2, nf2c3
- Location
projects/dram_router/regress/test_oq_dram_sz_cpu
- Output
SUCCESS!
Both projects are based on DDR2 Block Data Read Write module. This module provides a block read/write interface to user datapath pipeline.
The block read/write module takes 2034 bytes in each read/write. That requires the user datapath side to buffer the packets until the data exceeds this threshold. We implemented the buffer with Block RAM (BRAM).
For DRAM router, besides 8 DRAM queues, some extra modules are needed to coordinate different queues.
dram_queue_arbiter is in charge of multiplex packets different into different DRAM output queues.
dram_interface_arbiter let different queues get the access to DDR2 Block Read/Write module in a round-robin fashion.
dram_queue_regs makes use of generic_regs of NetFPGA gateware to provide a clean and simple register interface for all queues.
- XAPP549 - DDR2 SDRAM Memory Interface for Virtex-II Pro FPGAs - Xilinx Application Note for implementing DDR2 memory interfaces
- Xilinx Memory Solutions - Information about interfacing with various memory types. Includes a link to the Memory Interface Generator (MIG User Guide inside .ZIP file)