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Port Aggregator

Project summary

Status :
Released
Version :
1.0
Authors :
Tatsuya Yabe
NetFPGA base source :
2.0

Introduction

This is a sample project using Vlan remover/adder and outport_aggregator modules. This project allows you to decouple each NetFPGA input/output queue from a physical NetFPGA MAC port. This project uses Vlan tag values instead of physical port number to identify its 'source port'. It translates each 'destination port' information into the corresponding Vlan tag (specified through registers) and uses only one actual output port for sending out packets.

You can use a set of vlan_adder, vlan_remover and outport_aggregator modules as a wrapper for your own project.

Note: Since this design aggregates four ports into one, there is a bandwidth limitation allowing 1Gbps for 4 physical ports.

Download

Install from NetFPGA Yum repository

  1. Install the NetFPGA Base Package

Obtain Project Tarball

Download from Here

Regression Tests

The regression tests verify the functionality of this project. In order to run the tests, you need to have the machine connected for the regression tests as stated in the Run Regression Tests section of the Guide.

Preparation

Before you run regression tests, perform following command to create necessary headers and libraries for the tests. (Usually this script runs automatically when you run a simulation or run 'make' to do synthesis and implementation.) 

 nf2_register_gen.pl --project port_aggregator

Run regression tests

type the following command to run the regression tests. 

 nf2_regress_test.pl --project port_aggregator

Regression Tests: details

Test 1: Simple loopback test

Name :
test_loopback_simple
Description :
This test checks the programmability of forwarding ports and functionality of the output port aggregation. In this test, packets are sent from a CPU port to the corresponding MAC port, which has been setup by writing a value to a register. Aggregation output port number is also specified via a register. Outgoing packets are loopbacked in external PHY chip and sent back to the same NetFPGA MAC port. And then the packets should be sent back to the same CPU port, which has also been setup via register. The test compares if the received packets are equal to the sent packets. It also checks if the packet count is correct. This test exercises all four physical ports. This test doesn't use external NIC.
Location
projects/port_aggregator/regress/test_loopback_simple
Output 
 SUCCESS!

Test 2: Incoming port checking test without VLAN tag

Name :
test_drop_novlan
Description :
This test checks the functionality of VLAN remover, where it drops incoming packets which don't have vlan tags. In this test, non-vlan packets are sent from an external NIC to the cabled NetFPGA port and then reaches to FPGA's MAC port. In the FPGA, the packets are discarded because packets don't have vlan tags. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/port_aggregator/regress/test_drop_novlan
Output 
 SUCCESS!

Test 3: Incoming port checking test with wrong VLAN tags

Name :
test_drop_wrongvlan
Description :
Same test as test_drop_novlan. In this test, test packets have VLAN tags but different from expected values setup via registers in the vlan remover module. As same as the test above, in this test the packets should be discarded.
Location
projects/port_aggregator/regress/test_drop_wrongvlan
Output 
 SUCCESS!

Test 4: Outgoing port aggregation test

Name :
test_inaggr_outrandom
Description :
This test checks the outport aggregation functionality. In this test, packets with appropriate VLAN tags (same values as set in registers in vlan_remover) are sent from an external NIC to NetFPGA port. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (same configuration as the other tests). Then all the packets will be aggregated in one port configured via a register, and send them out from it. The packets should be received on the other NIC port. The test compares if the recieved packets have expected VLAN tags and the other portions are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/port_aggregator/regress/test_inaggr_outrandom
Output 
 SUCCESS!

Test 5: Outgoing port aggregation with VLAN ID-modification test

Name :
test_inaggr_outmod
Description :
This test checks the 'VLAN tag modification' functionality in addition to the test 4 above. In this test, packets with VLAN tags are sent from an external NIC to NetFPGA port, just as same as the test above. In the FPGA, the packets are forwarded to the different NetFPGA port, which has been configured via registers (same configuration as the other tests). Then NetFPGA overrides VLAN tags from the received one to the one specified in the registers, and sends them out of single port after output port aggregation. The packets should be received on the other NIC port. The test compares if the received packets have VLAN tags which are modified and changed to the expected ones, and checks if the other portions are equal to the sent packets. It also checks if the packet count is correct. This test exercises nf2c0 and nf2c1 ports. This test uses external NIC.
Location
projects/port_aggregator/regress/test_inaggr_outmod
Output 
 SUCCESS!

Usage

Preparation

Edit register-configuration file: 

 cd projects/port_aggregator/sw/
 vi register_setup.sh

You will find 17 variables on the top part of the file. They are 8 registers for setup forwarding output-ports, 4 registers for VLAN tag description for input ports, 4 registers or VLAN tag description for output ports and one register for specifying the output port. See comments for each section and modify accordingly.

Cabling

Connect the cables as you described in the register setup file above.

Download bitfile

Download the project bitfile: 

 su 
 nf2_download port_aggregator.bit

Run the script

Run the script you have modified: 

 su
 cd projects/port_aggregator/sw/
 ./register_setup.sh

Now you are ready to use this design.

Design description

Base design

vlan_tag_handler

Modules added or changed from the base design

vlan_remover (modified)

This module is attached as the first module of user_data_path. This module passes through all the packets coming from CPU ports. If an incoming packet is not from CPU port, it checks if it has VLAN ethernet type (0x8100) and checks VLAN tag value. If tag is not found or is different from the values setup in the registers, it discards the packet. Otherwise, it strips VLAN ether type field and VLAN tag field (totally 4 octets). VLAN tag field is inserted in a module header right after the IOQ module header. It also recalculates the packet size and replaces values in IOQ module header. So now the VLAN information resides in a module header and the packet itself doesn't have VLAN tag.

outport_aggregator(new, based on rr_input_arbiter)

This module aggregates packets from four ports in one outgoing port. The output port must be specified via a register. It inputs data from all four ports in parallel and choose one of them at a time in a round robin fashion. Now the data from four ports are aggregated in one queue. The data are copied and send out to all four output ports, but this module activates control signals of one output port (specified via a register).

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