axi4-lite
Here are 20 public repositories matching this topic...
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
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May 4, 2024 - SystemVerilog
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
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Sep 15, 2022 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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May 4, 2024 - SystemVerilog
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
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Oct 13, 2020 - C++
OLED driver demo running on ZedBoard
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Jun 24, 2018 - PHP
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
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Jul 15, 2016 - Tcl
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
HLS for Networks-on-Chip
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Feb 18, 2021 - C++
AXI4 and AXI4-Lite interface definitions
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Sep 20, 2020 - SystemVerilog
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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Jun 10, 2024 - VHDL
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jun 7, 2024 - SystemVerilog
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