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Improve code related to memory attributes #336

@sandrine-bailleux-arm

Description

@sandrine-bailleux-arm

This issue lists a number of improvements that the generic code related to memory attributes could benefit from.

The generic code currently defines 3 types of memory:

  • DEVICE_nGnRnE
  • DEVICE_nGnRE
  • normal memory

include/lib/aarch64/arch.h defines the memory attributes index field for MAIR_EL3 as well as the memory attribute encodings corresponding to each one of these AttrIndx values in a translation table entry:

  • ATTR_SO_INDEX == 2, which means that attribute index 2 in MAIR_EL3 corresponds to Strongly-Ordered memory (the old terminology for DEVICE_nGnRnE memory). The corresponding memory attributes are encoded by ATTR_SO == 0x0.
  • Similarly, ATTR_DEVICE_INDEX == 1 and ATTR_DEVICE == 0x4, which means that index 1 in MAIR_EL3 corresponds to Device memory (the old terminology for DEVICE_nGnRE memory) and its attributes are encoded as 0x4.
  • Similarly, ATTR_IWBWA_OWBWA_NTR_INDEX == 0 and ATTR_IWBWA_OWBWA_NTR == 0xff, which means that index 0 in MAIR_EL3 corresponds to normal memory and its attributes are encoded as 0xff.

There are a few issues with this code:

  • It is not documented. We should add some comments, or maybe explain it in the Firmware Design doc.
  • Some of the #defines names use the old ARM terminology. In the ARMv8-A architecture, "strongly-ordered" memory doesn't exist anymore, it's called "Device-nGnRnE" now. Similarly, "device" memory is too vague, as there several flavours of device memory. What used to be called just "device" memory is now more precisely "Device-nGnRE" memory. See section "E2.8.2 Device memory" in the ARMv8 ARM (ARM DDI 0487A.h).
  • The "Device-nGnRnE"/"Strongly-ordered" memory type is not actually used in the Trusted Firmware at the moment. The ATTR_SO_INDEX and ATTR_SO #defines should be removed to avoid any confusion.
  • The attribute indexes (1 for DEVICE_nGnRE and 0 for normal memory) should not be defined in include/lib/aarch64/arch.h, as these are not values defined by the architecture. Instead, they should be moved to plat/common/aarch64/plat_common.c, as they constitute the default memory types that most platforms would continue to use, but still allow platform ports to define alternative memory types.

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