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Merged
merged 4 commits into from
Sep 9, 2019
Merged

Kinetis update to fix tickless #11412

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6eca8d2
MCUXpresso: Change the Kinetis deep sleep implementation
mmahadevan108 Sep 4, 2019
e65012e
MCUXpresso: Update the Kinetis Serial driver for MBED_TICKLESS
mmahadevan108 Sep 4, 2019
b30e294
MCUXpresso: Change the MXRT deep sleep implementation
mmahadevan108 Sep 4, 2019
31da8ff
MCUXpresso: Update the MXRT Serial driver for MBED_TICKLESS
mmahadevan108 Sep 4, 2019
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52 changes: 46 additions & 6 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ static UART_Type *const uart_addrs[] = UART_BASE_PTRS;
/* Array of UART bus clock frequencies */
static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS;


int stdio_uart_inited = 0;
serial_t stdio_uart;

Expand Down Expand Up @@ -340,14 +339,55 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
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Personally, I'd be inclined to pare this down to more like:

static bool serial_is_enabled(uint32_t uart_index)
{
    switch (uart_index) {
        case 0:
            return SIM->SCGC4 & SIM_SCGC4_UART0_MASK;
        default:
            return false;
    }
}

Let bool take the strain. But this is fine.

break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT;
break;
default:
break;
}

return clock_enabled;
}

bool serial_check_tx_ongoing()
{
UART_Type *base = uart_addrs[uart_index];
UART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
51 changes: 46 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -332,14 +332,55 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART0_MASK) >> SIM_SCGC2_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART1_MASK) >> SIM_SCGC2_LPUART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART2_MASK) >> SIM_SCGC2_LPUART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART3_MASK) >> SIM_SCGC2_LPUART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART4_MASK) >> SIM_SCGC2_LPUART4_SHIFT;
break;
default:
break;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
return clock_enabled;
}

bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
42 changes: 37 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -288,14 +288,46 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
default:
break;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
return clock_enabled;
}

bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
42 changes: 37 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -300,14 +300,46 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
default:
break;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
return clock_enabled;
}

bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
45 changes: 40 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -328,14 +328,49 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART2_MASK) >> SIM_SCGC5_LPUART2_SHIFT;
break;
default:
break;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
return clock_enabled;
}

bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
45 changes: 40 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -327,14 +327,49 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi

#endif

void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
default:
break;
}

/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
return clock_enabled;
}

bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;

for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}

return uart_tx_ongoing;
}

#endif
25 changes: 20 additions & 5 deletions targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -282,14 +282,29 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}

void serial_wait_tx_complete(uint32_t uart_index)
bool serial_check_tx_ongoing()
{
LPUART_Type *base = uart_addrs[uart_index];
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
int clock_enabled = 0;

/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
/* First check if UART is enabled */
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;

if (!clock_enabled) {
/* UART is not enabled return */
return uart_tx_ongoing;
}

base = uart_addrs[i];

/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
}

return uart_tx_ongoing;
}

#endif
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