Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

STM32F4 UART issue when parity enabled #12611

Merged
merged 1 commit into from
Mar 13, 2020

Conversation

jeromecoutant
Copy link
Collaborator

Summary of changes

Fixes #11277

See STM32F429 Reference Manual:
Bits 8:0 DR[8:0]: Data value
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

Impact of changes

Migration actions required

Documentation


Pull request type

[x] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

Test results

FPGA tests updated, pull request is on going.

[] No Tests required for this change (E.g docs only update)
[x] Covered by existing mbed-os tests (Greentea or Unittest)
[] Tests / results supplied as part of this PR

Reviewers

@ARMmbed/team-st-mcd


Bits 8:0 DR[8:0]: Data value
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
@ciarmcom ciarmcom requested a review from a team March 10, 2020 18:00
@ciarmcom
Copy link
Member

@jeromecoutant, thank you for your changes.
@ARMmbed/mbed-os-maintainers please review.

@adbridge
Copy link
Contributor

CI started

@mbed-ci
Copy link

mbed-ci commented Mar 12, 2020

Test run: SUCCESS

Summary: 8 of 8 test jobs passed
Build number : 1
Build artifacts

@adbridge adbridge merged commit d61187c into ARMmbed:master Mar 13, 2020
@jeromecoutant jeromecoutant deleted the PR_UART_PARITY branch March 13, 2020 11:49
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

FPGA shield uart test
4 participants