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Add support for STEVAL-3DP001V1 board #6102

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merged 1 commit into from Mar 7, 2018

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@daid
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daid commented Feb 15, 2018

Description

This board is available from ST directly: http://www.st.com/en/evaluation-tools/steval-3dp001v1.html
And is interesting due to having stepper motor driver chips on the board itself. Which has uses beyond 3D printing, but also can be used in other robotics projects.

This board has an STM32F401VE chip. This support is based on the NUCLEO-F401RE board. Which has the same amount of flash/ram but less pins available on the chip. So it's pretty much a copy of the F401RE, with added pin definitions.

My biggest surprise was the addition I had to do in mbed_rtx. Maybe that defined() check can be changed into TARGET_STM32F401xE instead of one for TARGET_STM32F401VE and TARGET_STM32F401RE, as the whole E series has the same amount of RAM. But my experience with the STM32 chips is to limited so far to really make that call.

Status

READY

Related pull requests

Note that there is no automatic identification for this board. But it does have an integrated st-link. See #6000 for details on that.

@mbed-ci

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mbed-ci commented Feb 15, 2018

--none--

@daid

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daid commented Feb 15, 2018

For reference, this is the diff between the NUCLEO_F401RE and the STEVAL-3DP001V1 boards:

diff TARGET_NUCLEO_F401RE/ TARGET_STEVAL_3DP001V1/ -u
diff -u TARGET_NUCLEO_F401RE/PeripheralPins.c TARGET_STEVAL_3DP001V1/PeripheralPins.c
--- TARGET_NUCLEO_F401RE/PeripheralPins.c       2018-02-14 15:45:55.142291800 +0100
+++ TARGET_STEVAL_3DP001V1/PeripheralPins.c     2018-02-14 17:32:09.652789800 +0100
@@ -88,7 +88,7 @@
     {PB_3,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
     {PB_4,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
     {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
     {NC,    NC,    0}
 };
@@ -96,7 +96,7 @@
 MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
     {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
     {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
     {NC,    NC,    0}
 };
@@ -120,8 +120,8 @@
 #endif
     {PA_5,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
     {PA_6,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
-    {PA_7,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
-    {PA_7_ALT0,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+    {PA_7,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PA_7_ALT0,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
     {PA_8,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
     {PA_9,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
     {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
@@ -132,25 +132,41 @@
     {PB_0_ALT0,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
     {PB_1,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
     {PB_1_ALT0,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
-    {PB_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - ARDUINO
-    {PB_4,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1 - ARDUINO
+    {PB_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
     {PB_5,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-    {PB_6,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1 - ARDUINO
+    {PB_6,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
     {PB_7,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
     {PB_8,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
     {PB_8_ALT0,  PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
     {PB_9,  PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
     {PB_9_ALT0,  PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
-    {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - ARDUINO
+    {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
     {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
     {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
     {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N

     {PC_6,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-    {PC_7,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 - ARDUINO
+    {PC_7,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
     {PC_8,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
     {PC_9,  PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4

+    {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+    {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+    {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+
+    {PE_5,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)},  // TIM9_CH1
+    {PE_6,  PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)},  // TIM9_CH2
+
+    {PE_8,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PE_9,  PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+    {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+    {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+    {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
     {NC,    NC,    0}
 };

@@ -162,6 +178,7 @@
     {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {NC,    NC,     0}
 };

@@ -171,18 +188,21 @@
     {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {NC,    NC,     0}
 };

 MBED_WEAK const PinMap PinMap_UART_RTS[] = {
     {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {NC,    NC,     0}
 };

 MBED_WEAK const PinMap PinMap_UART_CTS[] = {
     {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {NC,    NC,     0}
 };

@@ -195,6 +215,7 @@
     {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_6,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
     {NC,    NC,    0}
 };

@@ -205,6 +226,7 @@
     {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PE_5,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
     {NC,    NC,    0}
 };

@@ -215,6 +237,8 @@
     {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
     {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_2,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
     {NC,    NC,    0}
 };

@@ -225,5 +249,6 @@
     {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
     {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
     {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PE_4,  SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
     {NC,    NC,    0}
 };
diff -u TARGET_NUCLEO_F401RE/PinNames.h TARGET_STEVAL_3DP001V1/PinNames.h
--- TARGET_NUCLEO_F401RE/PinNames.h     2018-02-14 15:45:55.142291800 +0100
+++ TARGET_STEVAL_3DP001V1/PinNames.h   2018-02-14 16:00:10.340229100 +0100
@@ -105,7 +105,39 @@
     PC_14 = 0x2E, // Connected to RCC_OSC32_IN
     PC_15 = 0x2F, // Connected to RCC_OSC32_OUT

+    PD_0  = 0x30,
+    PD_1  = 0x31,
     PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,

     PH_0  = 0x70, // Connected to RCC_OSC_IN
     PH_1  = 0x71, // Connected to RCC_OSC_OUT
@@ -143,12 +175,12 @@
 #ifdef MBED_CONF_TARGET_STDIO_UART_TX
     STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
 #else
-    STDIO_UART_TX = PA_2,
+    STDIO_UART_TX = PA_9,
 #endif
 #ifdef MBED_CONF_TARGET_STDIO_UART_RX
     STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
 #else
-    STDIO_UART_RX = PA_3,
+    STDIO_UART_RX = PA_10,
 #endif

     // Generic signals namings
@@ -157,7 +189,7 @@
     LED3        = PA_5,
     LED4        = PA_5,
     LED_RED     = LED1,
-    USER_BUTTON = PC_13,
+    USER_BUTTON = PE_7,
     // Standardized button names
     BUTTON1 = USER_BUTTON,
     SERIAL_TX   = STDIO_UART_TX,
@0xc0170

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0xc0170 commented Feb 15, 2018

Does it have same stlink firmware as other boards (those we have supported like nucleo f401re or similar)?

@ARMmbed/team-st-mcd Please review

@daid

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daid commented Feb 15, 2018

@0xc0170 I think it's the same firmware. It acts the same as the Nucleo F303RE boards we have here. With 1 exception, that the htm file is missing on the mass storage device. The virtual COM port is there, and we can debug the board as well with the standard tools.

{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
{NC, NC, 0}

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

Please add for MOSI:
{PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}
{PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}

{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
{NC, NC, 0}
};

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

Please add for MISO:
{PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}

{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
{NC, NC, 0}

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

Please add for SCLK:
{PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}

{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
{NC, NC, 0}

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

Please add for SSEL:
{PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}

};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO

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jeromecoutant Feb 15, 2018

Contributor

I think Arduino comment can be removed ?

@@ -69,6 +69,7 @@
#define INITIAL_SP (0x20014000UL)
#elif (defined(TARGET_STM32F401RE) ||\
defined(TARGET_STM32F401VE) ||\

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

I agree that this patch could be avoided if we change:
defined(TARGET_STM32F401xE)

"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

I don't know the board, but is HSE from ST Link connected ?
Or are you using HSI ?

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@daid

daid Feb 16, 2018

Contributor

My knowledge here is lacking. So not sure what you mean (I just copied this piece of code from the NUCLEO_F303RE).
There is a 25Mhz xtal connected to PH0/PH1. That seems to be the only clock connected.

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@jeromecoutant

jeromecoutant Feb 16, 2018

Contributor

OK
Could you check (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) value ?
I expect 0, ie. HSI, which means that HSE configuration has failed.

MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
#ifdef MBED_CONF_TARGET_STDIO_UART_TX

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@jeromecoutant

jeromecoutant Feb 15, 2018

Contributor

As default STDIO_UART_TX and STDIO_UART_RX is not the same as Nucleo F401,
these ifdef are not correct.

I think you should remove them and keep all the pins available for application.
(and remove Connected to STDIO_UART_TX/RX comments)

@jeromecoutant

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jeromecoutant commented Feb 15, 2018

You can also check some mbed-os/tools files:

  • build_travis.py: to add your target in the ARM CI check
  • export/xx : to enable the export feature

@cmonr cmonr added needs: work and removed needs: review labels Feb 15, 2018

@jeromecoutant

I don't have the board, I can't try, but let me know if it is working like this.
I expect (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) value becomes 0x400000

"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
}

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jeromecoutant Feb 16, 2018

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Can you try:

  • "help": "Mask value : USE_PLL_HSE_XTAL | USE_PLL_HSI"
  • "value": "USE_PLL_HSE_XTAL"

And add:

  • "macros_add": ["HSE_VALUE=25000000"],

As it seems there is no external 32KHz clock on this boards, you should also add:

  • "overrides": {"lse_available": 0}
RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {

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With the new value in the targets.json file, set:

  • PLLM=25
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {

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Update comment as external clock is 25 MHz

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daid commented Feb 21, 2018

Ok, I fixed the clock config. I think I understand how it works now. (Problem was that the example for this board doesn't use the external XTAL at all. Which threw me on the wrong path)
I haven't validated yet if it is using it now.

Still need to add it to tools/export, but not sure where.

}
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
RCC_OscInitStruct.PLL.PLLM = 24; // VCO input clock = 1 MHz (24 MHz / 8)

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jeromecoutant Feb 21, 2018

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Clock is 25 MHz, not 24 ?

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Feel like an idiot now. Yes, it's 25Mhz. Wanting to go a bit too fast, and doing too much as once...

I could also use HSE_VALUE / 1000000 now right?

@0xc0170 0xc0170 added needs: review and removed needs: work labels Feb 21, 2018

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0xc0170 commented Feb 22, 2018

@daid Can you review Travis failure ? Related to this target

@0xc0170 0xc0170 added needs: work and removed needs: review labels Feb 22, 2018

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jeromecoutant commented Feb 22, 2018

Hi

Can you review Travis failure ? Related to this target

I am checking also on my side.
It seems that there is a ST issue :-(

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jeromecoutant commented Feb 22, 2018

@daid
please add a patch in

#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */

#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */

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daid commented Feb 22, 2018

It indeed seems GPIO_AF5_SPI3 is missing from the ST-HAL.

Do we add that ourselves? Do we notify ST? Or do we implement a work-around?

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daid commented Feb 22, 2018

@jeremybrodt Shouldn't the define also be added in the IS_GPIO_AF macro? (Not that that macro behavior would really change, as the number 5 is already in there. Not sure what the use of that macro is...)

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jeromecoutant commented Feb 22, 2018

Shouldn't the define also be added in the IS_GPIO_AF macro?

Yes you could, but this macro is compiled only if USE_FULL_ASSERT is defined,
which is not the default case.

Note that ST driver team has confirmed the issue,
official patch will be provided in the next ST Cube update.

Thx

@0xc0170 0xc0170 added needs: CI and removed needs: work labels Feb 22, 2018

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0xc0170 commented Feb 22, 2018

/morph build

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mbed-ci commented Feb 22, 2018

Build : SUCCESS

Build number : 1222
Build artifacts/logs : http://mbed-os.s3-website-eu-west-1.amazonaws.com/?prefix=builds/6102/

Triggering tests

/morph test
/morph uvisor-test
/morph export-build
/morph mbed2-build

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cmonr commented Feb 27, 2018

@daid Heads up, it looks like this will need to be rebased.

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daid commented Feb 27, 2018

@cmor Shall I squash the commits as well? Makes for a cleaner history.

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cmonr commented Feb 27, 2018

@daid No need for the squash, since this PR still has what I would consider to be a small amount of commits.

However, I will have to ask you to undo your last commit (Merge branch 'master' into master) and do a rebase instead. If you take a look at what that commit does to the files by clicking the link in GitHub, you'll see something like "Showing 831 changed files with 61,529 additions and 26,619 deletions.", and this throws off our release process massively. A rebase instead changes the head of your PR branch to point to the master head, and replays your changes on top of that.

@cmonr cmonr added needs: work and removed needs: CI labels Feb 27, 2018

Add support for STEVAL-3DP001V1 board, which has an STM32F401VE chip.…
… This support is based on the NUCLEO-F401RE board. Which has the same amount of flash/ram but less pins available on the chip.
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daid commented Feb 28, 2018

As I needed to rebase anyhow (I incorrectly thought the github webinterface did this for me) I did squash. For my own practice of git.

@cmonr cmonr added needs: CI and removed needs: work labels Feb 28, 2018

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cmonr commented Feb 28, 2018

@jeromecoutant Think you could give your OK again? The rebase + squash invalidated the last review.

/morph build

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cmonr commented Mar 1, 2018

/morph build

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cmonr approved these changes Mar 1, 2018

@adbridge adbridge added needs: review and removed needs: CI labels Mar 1, 2018

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cmonr commented Mar 6, 2018

/morph build

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cmonr commented Mar 6, 2018

@studavekar This one worked as well, but looks like it had issues.

@cmonr cmonr added needs: CI and removed needs: review labels Mar 6, 2018

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mbed-ci commented Mar 6, 2018

Build : SUCCESS

Build number : 1351
Build artifacts/logs : http://mbed-os.s3-website-eu-west-1.amazonaws.com/?prefix=builds/6102/

Triggering tests

/morph test
/morph uvisor-test
/morph export-build
/morph mbed2-build

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studavekar commented Mar 6, 2018

/morph mbed2-build

@cmonr cmonr merged commit 8a7b390 into ARMmbed:master Mar 7, 2018

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