VLSI_Design-Implementation

This repo is "NTHU VLSI System Design and Implementation" course project.

Design Environment

NCverilog & nWave

Lab01 Ping-Pong Counter

Design a 5-bit pingpong counter with inputs and output ports specification as requirement.

Lab02 GCD Engine

Design a calculator to get the greatest common divisor of two integers.
PartA: input two 8-bit integers while the input ports of A&B are also 8-bit
PartB: input two 16-bit integers while the input ports of A&B are restricted by 8-bit

Lab03 Parameterized Ping-Pong Counter

Redesign Lab01 and parameterize all constants.

• test pattern 04 with default 15 out signal errors!

Project01 Local Median Filter Engine

Design a median filter engine to calculate any 2D grayscale image input, the mask size of the median filter is 7x7.

Lab04 APR Practice

Use the given file to implement block level APR by toturial flow

Project02 Sample Adaptive Offset Filter Engine

Design a SAO filter engine to calculate any 2D grayscale image input.