NEON optimizations for ZIP reading (reconstruct and interleave) #1348
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Pretty much straight copies from the SSE2/SSE4 SIMD code, just changed for NEON. Reading 310Mpix worth of ZIP compressed EXR files into memory, on Apple M1 Max (Clang 14, RelWithDebInfo build config): 7.50s -> 5.52s. "reconstruct" part goes 1.55s -> 0.35s, "interleave" 0.80s -> 0.04s. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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…emySoftwareFoundation#1348) Pretty much straight copies from the SSE2/SSE4 SIMD code, just changed for NEON. Reading 310Mpix worth of ZIP compressed EXR files into memory, on Apple M1 Max (Clang 14, RelWithDebInfo build config): 7.50s -> 5.52s. "reconstruct" part goes 1.55s -> 0.35s, "interleave" 0.80s -> 0.04s. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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Pretty much straight copies from the SSE2/SSE4 SIMD code, just changed for NEON. Reading 310Mpix worth of ZIP compressed EXR files into memory, on Apple M1 Max (Clang 14, RelWithDebInfo build config): 7.50s -> 5.52s. "reconstruct" part goes 1.55s -> 0.35s, "interleave" 0.80s -> 0.04s. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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…ch64) only Should fix AcademySoftwareFoundation#1365. Recent PR (AcademySoftwareFoundation#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms.
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…ch64) only Should fix AcademySoftwareFoundation#1365. Recent PR (AcademySoftwareFoundation#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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…ch64) only (#1366) Should fix #1365. Recent PR (#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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Mar 26, 2023
…ch64) only (AcademySoftwareFoundation#1366) Should fix AcademySoftwareFoundation#1365. Recent PR (AcademySoftwareFoundation#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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Mar 26, 2023
…ch64) only (AcademySoftwareFoundation#1366) Should fix AcademySoftwareFoundation#1365. Recent PR (AcademySoftwareFoundation#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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Mar 28, 2023
…ch64) only (#1366) Should fix #1365. Recent PR (#1348) added NEON accelerated code paths for ZIP filtering. But that code uses several instructions that are ARMv8 (aarch64) only, and thus fail building on 32-bit ARM (armv7) platforms. Make these optimizations only kick in when building for 64-bit ARM platforms. Signed-off-by: Aras Pranckevicius <aras@nesnausk.org>
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Pretty much straight copies from the SSE2/SSE4 SIMD code, just changed for NEON.
Reading 310Mpix worth of ZIP compressed EXR files into memory, on Apple M1 Max (Clang 14, RelWithDebInfo build config): 7.50s -> 5.52s.
"reconstruct" part goes 1.55s -> 0.35s, "interleave" 0.80s -> 0.04s.