Slightly modernize Verilog, take 2

doc/user_guide/user_guide.tex

@@ -1627,14 +1627,12 @@ \subsection{Verilog back-end}
 back end.
 \index{-remove-unused-modules@\te{-remove-unused-modules} (compiler
 flag)}
-\index{-v95@\te{-v95} (compiler flag)}
 \index{-remove-dollar@\te{-remove-dollar} (compiler flag)}
 \index{-unspecified-to@\te{-unspecified-to} (compiler flag)}
 \index{-Xv@\te{-Xv} (compiler flag)}
 \index{-verilog-filter@\te{-verilog-filter} (compiler flag)}
 \begin{centerboxverbatim}
 -remove-unused-modules  remove unconnected modules from the Verilog
--v95                    generate strict Verilog 95 code
 -unspecified-to val     remaining unspecified values are set to:
                          'X', '0', '1', 'Z', or 'A'
 -remove-dollar          remove dollar signs from Verilog identifiers
@@ -1649,14 +1647,6 @@ \subsection{Verilog back-end}
 should be used on modules undergoing synthesis, and not be used for
 testbench modules.
 
-The {\bf\tt -v95} flag restricts the Verilog output to pure Verilog-95.
-By default, the Verilog output uses features which are not in the
-Verilog-95 standard.  These features include passing module
-parameters by name and use of the {\tt \$signed} system task for formatting
-{\tt \$display} output.  When the {\tt -v95} flag is turned on, uses
-of these features are removed, but comments are left in the Verilog
-indicating the parameter names or system tasks which were removed.
-
 The {\bf\tt -unspecified-to val} flag defines the value
 which any remaining unspecified values should be tied to.  The valid
 set of values are: {\tt X}, {\tt 0}, {\tt 1}, {\tt Z}, or {\tt A},
@@ -3442,14 +3432,14 @@ \subsubsection{State elements}
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else // no BSV_NO_INITIAL_BLOCKS
-// synopsys translate_off
+`ifndef SYNTHESIS
 initial
 begin
   reg_1 = 51'h2AAAAAAAAAAAA;
   reg_2 = 51'h2AAAAAAAAAAAA;
   reg_3 = 51'h2AAAAAAAAAAAA;
 end
-// synopsys translate_on
+`endif // SYNTHESIS
 `endif // BSV_NO_INITIAL_BLOCKS
 \end{centerboxverbatim}
 %    \caption{\label{reg-ver-fig}Generated Verilog for Register
@@ -3652,7 +3642,7 @@ \subsubsection{Other signals}
 	  WILL_FIRE_RL_flip or
 	  reg_1 or WILL_FIRE_RL_sub or MUX_reg_2$write_1__VAL_3)
   begin
-    case (1'b1) // synopsys parallel_case
+    (* parallel_case *) case (1'b1)
       EN_start: reg_2$D_IN = start_num2;
       WILL_FIRE_RL_flip: reg_2$D_IN = reg_1;
       WILL_FIRE_RL_sub: reg_2$D_IN = MUX_reg_2$write_1__VAL_3;
@@ -3672,7 +3662,7 @@ \subsubsection{Other signals}
     if (reg_2$EN) reg_2 <= `BSV_ASSIGNMENT_DELAY reg_2$D_IN;
   end
 
-  // synopsys translate_off
+  `ifndef SYNTHESIS
   `ifdef BSV_NO_INITIAL_BLOCKS
   `else // not BSV_NO_INITIAL_BLOCKS
   initial
@@ -3681,7 +3671,7 @@ \subsubsection{Other signals}
     reg_2 = 51'h2AAAAAAAAAAAA;
   end
   `endif // BSV_NO_INITIAL_BLOCKS
-  // synopsys translate_on
+  `endif // SYNTHESIS
 endmodule  // mkGCD
 
 \end{libverbatim}

src/Verilog.Vivado/BRAM1.v

@@ -32,7 +32,7 @@ module BRAM1(CLK,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    integer                        i;
    initial
    begin : init_block
@@ -42,7 +42,7 @@ module BRAM1(CLK,
       DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    always @(posedge CLK) begin

src/Verilog.Vivado/BRAM1BE.v

@@ -35,7 +35,7 @@ module BRAM1BE(CLK,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
       integer   i;
@@ -45,7 +45,7 @@ module BRAM1BE(CLK,
       DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    generate

src/Verilog.Vivado/BRAM1BELoad.v

@@ -34,7 +34,7 @@ module BRAM1BELoad(CLK,
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
 `ifdef BSV_NO_INITIAL_BLOCKS
@@ -43,7 +43,7 @@ module BRAM1BELoad(CLK,
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
    initial
    begin : init_rom_block

src/Verilog.Vivado/BRAM1Load.v

@@ -32,7 +32,7 @@ module BRAM1Load(CLK,
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
 `ifdef BSV_NO_INITIAL_BLOCKS
@@ -41,7 +41,7 @@ module BRAM1Load(CLK,
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
    initial
    begin : init_rom_block

src/Verilog.Vivado/BRAM2.v

@@ -47,7 +47,7 @@ module BRAM2(CLKA,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    integer                        i;
    initial
    begin : init_block
@@ -59,7 +59,7 @@ module BRAM2(CLKA,
       DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    always @(posedge CLKA) begin

src/Verilog.Vivado/BRAM2BE.v

@@ -49,7 +49,7 @@ module BRAM2BE(CLKA,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    integer                        i;
    initial
    begin : init_block
@@ -61,7 +61,7 @@ module BRAM2BE(CLKA,
       DOB_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    // PORT A

src/Verilog.Vivado/BRAM2BELoad.v

@@ -49,7 +49,7 @@ module BRAM2BELoad(CLKA,
    reg [DATA_WIDTH-1:0]           DOB_R;
    reg [DATA_WIDTH-1:0]           DOB_R2;
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
 `ifdef BSV_NO_INITIAL_BLOCKS
@@ -60,7 +60,7 @@ module BRAM2BELoad(CLKA,
       DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
    initial
    begin : init_rom_block

src/Verilog.Vivado/BRAM2Load.v

@@ -47,7 +47,7 @@ module BRAM2Load(CLKA,
    reg [DATA_WIDTH-1:0]           DOA_R2;
    reg [DATA_WIDTH-1:0]           DOB_R2;
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
 `ifdef BSV_NO_INITIAL_BLOCKS
@@ -58,7 +58,7 @@ module BRAM2Load(CLKA,
       DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
    initial
    begin : init_rom_block

src/Verilog.Vivado/GatedClock.v

@@ -79,14 +79,14 @@ module GatedClock(
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
       begin
 	 #0 ;
          new_gate = 1'b0 ;
 	 COND_reg = 1'b0 ;
       end // initial begin
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // BSV_NO_INITIAL_BLOCKS
 
 endmodule // GatedClock

src/Verilog.Vivado/MakeClock.v

@@ -111,15 +111,15 @@ module MakeClock ( CLK, RST,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial begin
       #0 ;
       current_clk  = 1'b0 ;
       current_gate = 1'b1 ;
       new_gate     = 1'b1 ;
       CLK_VAL_OUT  = 1'b0;
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // BSV_NO_INITIAL_BLOCKS
 
 endmodule

src/Verilog.Vivado/RegFile.v

@@ -51,15 +51,15 @@ module RegFile(CLK,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
      begin : init_block
         integer                     i;          // temporary for generate reset value
         for (i = lo; i <= hi; i = i + 1) begin
            arr[i] = {((data_width + 1)/2){2'b10}} ;
         end
      end // initial begin
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // BSV_NO_INITIAL_BLOCKS
 
 
@@ -75,7 +75,7 @@ module RegFile(CLK,
    assign D_OUT_4 = arr[ADDR_4];
    assign D_OUT_5 = arr[ADDR_5];
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    always@(posedge CLK)
      begin : runtime_check
         reg enable_check;
@@ -96,6 +96,6 @@ module RegFile(CLK,
                 $display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
            end
      end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
 endmodule

src/Verilog.Vivado/SizedFIFO.v

@@ -84,7 +84,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else // not BSV_NO_INITIAL_BLOCKS
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
      begin : initial_block
         integer   i;
@@ -101,7 +101,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
              arr[i]   = D_OUT ;
           end
      end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // BSV_NO_INITIAL_BLOCKS
 
 
@@ -209,7 +209,7 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
          end // else: !if(RST == `BSV_RESET_VALUE)
      end // always @ (posedge CLK)
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    always@(posedge CLK)
      begin: error_checks
         reg deqerror, enqerror ;
@@ -230,9 +230,9 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
                 end
            end
      end // block: error_checks
-   // synopsys translate_on
+`endif // SYNTHESIS
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    // Some assertions about parameter values
    initial
      begin : parameter_assertions
@@ -254,6 +254,6 @@ module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
         if ( ok == 0 ) $finish ;
 
       end // initial begin
-   // synopsys translate_on
+`endif // SYNTHESIS
 
 endmodule

src/Verilog/BRAM1.v

@@ -31,7 +31,7 @@ module BRAM1(CLK,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    integer                        i;
    initial
    begin : init_block
@@ -41,7 +41,7 @@ module BRAM1(CLK,
       DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    always @(posedge CLK) begin

src/Verilog/BRAM1BE.v

@@ -34,7 +34,7 @@ module BRAM1BE(CLK,
 
 `ifdef BSV_NO_INITIAL_BLOCKS
 `else
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
       integer   i;
@@ -44,7 +44,7 @@ module BRAM1BE(CLK,
       DO_R  = { ((DATA_WIDTH+1)/2) { 2'b10 } };
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
 
    generate

src/Verilog/BRAM1BELoad.v

@@ -33,7 +33,7 @@ module BRAM1BELoad(CLK,
    reg [DATA_WIDTH-1:0]           DO_R;
    reg [DATA_WIDTH-1:0]           DO_R2;
 
-   // synopsys translate_off
+`ifndef SYNTHESIS
    initial
    begin : init_block
 `ifdef BSV_NO_INITIAL_BLOCKS
@@ -42,7 +42,7 @@ module BRAM1BELoad(CLK,
       DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
 `endif // !`ifdef BSV_NO_INITIAL_BLOCKS
    end
-   // synopsys translate_on
+`endif // SYNTHESIS
 
    initial
    begin : init_rom_block