BLogic MCU v1.0

First public release of BLogic MCU, the RISC-V microcontroller designed by BLogic Mikroelektronik
(Ostim Technical University) for the TEKNOFEST 2026 Chip Design Competition.

The RTL is the configuration delivered to the competition: CV32E40P (RV32IMC) on an AXI4 fabric,
UART x2, GPIO, timer, I2C, QSPI flash boot, JTAG debug and the TFLite Micro Speech accelerator.
The repository exactly as submitted is preserved under the tag teknofest-final.

Release files

File	Content
asic-results-v1.0.tar.gz	Outputs of the signed-off sky130 run RUN_hold035_2026-09-09: GDS (Magic and KLayout), ODB, Magic database, DEF, SDF, SPEF (min, nom, max), SPICE and netlists. Unpack in the repository root, or run bash asic/fetch_results.sh, which also checks every file against the committed SHA-256 values.
asic_top-v1.0.gds.gz	The final GDS on its own.
SHA256SUMS	Checksums of the files above.

The signoff reports remain in the repository under asic/reports/.

Simulation image

docker run --rm ghcr.io/blogic-microelectronic/blogic-mcu:v1.0

runs a boot test and one inference on the accelerator in the Verilator model. Any make target can be
given as the command.

Status

• FPGA: Digilent Genesys 2 (Kintex-7), 50 MHz, timing met.
• ASIC: sky130, DRC 0, LVS match, gate-level simulation with SDF passing at the verified 27.0 MHz.
• Verification: 90.7 % line and 88.5 % branch coverage, riscv-arch-test 72 of 73 identical to Spike,
  UVM for five blocks. The simulation suite runs on every push in GitHub Actions.

Known deviations from the competition specification and the known limitations of the design are listed
in section 5.7 of docs/DOCUMENTATION.md.