Merge pull request #117 from DFiantHDL/i116

Fix #116

compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala

@@ -311,16 +311,24 @@ extension (refTW: DFNet.Ref)
       case _ => false
 
 extension (origVal: DFVal)
-  private def collectRelMembersRecur(includeOrigVal: Boolean)(using MemberGetSet): List[DFVal] =
-    if (origVal.isAnonymous && !origVal.isGlobal || includeOrigVal)
-      origVal :: origVal.getRefs.view.map(_.get).flatMap {
-        case dfVal: DFVal => dfVal.collectRelMembersRecur(false)
-        case _            => Nil
-      }.toList
+  private def collectRelMembersRecur(
+      forceIncludeOrigVal: Boolean
+  )(using MemberGetSet): List[DFVal] =
+    if (origVal.isAnonymous && !origVal.isGlobal || forceIncludeOrigVal)
+      origVal :: origVal.getRefs.view
+        .flatMap {
+          case _: DFRef.TypeRef => None
+          case r                => Some(r.get)
+        }
+        .flatMap {
+          case dfVal: DFVal => dfVal.collectRelMembersRecur(false)
+          case _            => Nil
+        }.toList
     else Nil
   @targetName("collectRelMembersDFVal")
   def collectRelMembers(includeOrigVal: Boolean)(using MemberGetSet): List[DFVal] =
     origVal.collectRelMembersRecur(includeOrigVal).reverse
+end extension
 
 extension (net: DFNet)
   @targetName("collectRelMembersDFNet")

compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala

@@ -65,33 +65,21 @@ case object ToED extends Stage:
                 rn.regAlias -> Patch.Remove()
               )
             )
-            @tailrec def getDeps(
-                leftMembers: List[DFMember],
-                handledMembers: Set[DFMember]
-            ): Set[DFMember] =
-              leftMembers match
-                case head :: last =>
-                  head match
-                    case dcl: DFVal.Dcl => getDeps(last, handledMembers)
-                    case _ if !handledMembers.contains(head) =>
-                      val moreMembers = head.getRefs.view.flatMap {
-                        case _: DFRef.TypeRef => None
-                        case r                => Some(r.get)
-                      }
-                      getDeps(last ++ moreMembers, handledMembers + head)
-                    case _ => getDeps(last, handledMembers)
-                case Nil => handledMembers
 
             def processMembers(list: List[DFMember]): List[DFMember] =
-              val processBlockAllMembersSet = list.view.flatMap {
+              val processBlockAllMembersSet: Set[DFMember] = list.view.flatMap {
                 case DesignParam(_)                 => None
                 case net: DFNet if net.isConnection => None
                 case net @ DFNet.Assignment(_, fromVal) if removedNets.contains(net) =>
-                  getDeps(List(fromVal), Set())
+                  fromVal.collectRelMembers(false)
                 case net: DFNet =>
-                  getDeps(List(net), Set())
+                  net :: net.collectRelMembers
                 case ch: DFConditional.Header if ch.dfType == DFUnit =>
-                  getDeps(List(ch), Set())
+                  ch.collectRelMembers(false)
+                case cb: DFConditional.Block =>
+                  cb.guardRef.get match
+                    case dfVal: DFVal => cb :: dfVal.collectRelMembers(false)
+                    case _            => List(cb)
                 case _ => None
               }.toSet
 

lib/src/test/scala/issues/IssueSpec.scala

@@ -0,0 +1,8 @@
+package issues
+
+import munit.*
+import dfhdl.*
+
+class IssuesSpec extends FunSuite:
+  test("i116 compiles with no exception"):
+    i116.GlobCounter(64).compile

lib/src/test/scala/issues/i116.scala

@@ -0,0 +1,55 @@
+// format: off
+package issues.i116
+
+import dfhdl.* 
+
+case class Test (
+  a : Bit <> VAL,
+  b : Bit <> VAL
+) extends Struct
+
+class GlobCounter (val width: Int <> CONST) extends RTDesign:
+  val req = Bit <> IN
+  val req2 = Bit <> IN
+  val t = Test <> IN
+  val t_b = Bit <> VAR
+  t_b := t.b
+  val t_int = Test <> VAR 
+  t_int := t
+
+  val cnt = UInt(width) <> OUT.REG init 0
+
+  if (t.a) {
+    if (t.b) { 
+        cnt.din := cnt + 1
+    }
+  }
+
+  if (req) {
+    if (t.b) { 
+        cnt.din := cnt + 1
+    }
+  }
+
+  if (t.a && t.b) {
+    cnt.din := cnt + 1
+  }
+
+  if (t.a) {
+    if (t_b) { 
+        cnt.din := cnt + 1
+    }
+  }
+
+  if (t_int.a) {
+    if (t_int.b) { 
+        cnt.din := cnt + 1
+    }
+  }
+
+  if (req) {
+    if (req2) {
+      cnt.din := cnt + 1
+    }
+  }
+end GlobCounter