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0.6.0 update batch #165

Merged
merged 167 commits into from
Aug 15, 2024
Merged

0.6.0 update batch #165

merged 167 commits into from
Aug 15, 2024

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soronpo
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@soronpo soronpo commented Aug 11, 2024

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@soronpo
move lib implementations to its own folder
87886ab
@soronpo
propagate tags through DFC
8ce08a0
@soronpo
propagate specific tags into DFC before creating values
c149f6f
@soronpo
enable referencing unreachable members for better meta-programming
ed1c256
@soronpo
some cleanup
4775610
@soronpo
fix DFType reference comparisons and getRefs
e22a88e
@soronpo
add length tests to vector assignments and comparisons
1dae551
@soronpo
add unreachable value elaboration tests
22943c5
@soronpo
enable another test in vectors
f8bfe98
@soronpo
fix DFC propagation of methods
bd352a9
@soronpo
docs: add global Verilog/VHDL switch
13135c2
@soronpo
preserve initialization for constant variables
12bfb89
@soronpo
docs: ALU cosmetic touchups
b52ce9d
@soronpo
handle unreachable type referenced value parameters by inlining them
d96de6b
@soronpo
make DFTypes accessible to implicit scope through ValueOf
72dbb80
@soronpo
prepare for version 3.5.0-RC2
38691a9
@soronpo
create preliminary generic rom in lib
ae8b49e
@soronpo
introduce FlattenMode to domains (no flattening stage yet)
2e36a2b
@soronpo
introduce RelatedDomain in RTDomain (not handled in stages yet) + min…
8ffa805 
…or error refactoring
@soronpo
change getRefs from def to lazy val
11ac61c
@soronpo
fix condition to allow dfc placement in designs that are inside domai…
9ce0e31 
…ns (which are anonymous classes)
@soronpo
fix bad context generation when owner definition has a context argume…
89ca6fa 
…nt (like in design companion constructors)
@soronpo
fix edge cases for non-RT domain top design with RT domains and Relat…
effc1d9 
…edDomains
@soronpo
fix printing of history aliases by looking at domain type of the alia…
1a7bc3a 
…s and not the relative value
@soronpo
fix ToED failing with reg on output of an internal design and better …
f5eca96 
…name suggestion
@soronpo
more correct name suggestion and special case PortByNameSelect
c2d313e
@soronpo
fix relative name printing
5770e5c
@soronpo
enable RelatedDomain of RTDesign
e7517d5
@soronpo
add RT domain derived dependency and elaboration checks
6072869
@soronpo
improved multi-RT domain support
0812ae7
@soronpo
refactored RT domain configuration
3d975c8
@soronpo
better printing alignment to remove outliers
338b245
@soronpo
better verilog port alignment printing
f220872
@soronpo
minor simplification to alignment
ba8986a
@soronpo
refactoring to NameRegAliases and ToED for simpler register represent…
f4fac78 
…ations
@soronpo
add TrueDPR example to documentation and CI
f23b04d
@soronpo
fix domain analysis for related domain dependent on its owner
30da783
@soronpo
fix internal related domain issue in ToED and relevant Patch issue ke…
4d36d84 
…eping a replaced member reference
@soronpo
using better traversal for ToED
7d4ff3e
@soronpo
turning on unreferenced anon sanity check and tagging stages that nul…
77fe1dd 
…lifies the fixing stage for that
@soronpo
better verilog port alignment around logic keyword
60ac40f
@soronpo
add register file example
fd8c4fd
@soronpo
removing accidental trace
de614fb
@soronpo
prepare for Scala 3.5.0: fix compiler warnings "Extension method XYZ …
2b12d42 
…will never be selected"
@soronpo
introduce sel select operation on a bit/boolean
bd83832
@soronpo
better tool execution on windows and add version reading
8e9e7f4
@soronpo
add version printing when installing verilator and ghdl
6610106
@soronpo
changing verilator linting according to version
053c704
@soronpo
add missing error printing
f4107fa
@soronpo
prefer exceptions during sbt test as well
71f5f55
@soronpo
belongs to previous commit
ae53ea6
@soronpo
refine sbt shell/test detection
f840997
@soronpo
update tool error printing
5ca1306
@soronpo
update tool installation to use oss-cad-suite
cd637c3
@soronpo
ci: run version separately
699260a
@soronpo
force exception on error in elaboration checks in case auto detection…
d9753ab 
… default does not work
@soronpo
fix bits repeat functionality in VHDL
efefe69
@soronpo
moving dfhdl defs/pkg files to an external resource file and separati…
e153a41 
…ng the project global from those contents
@soronpo
add support for Verilog Bin/Hex standard file initialization
81a09db
@soronpo soronpo merged commit a119bcf into main Aug 15, 2024
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@soronpo