GitHub - Danny552/Processor: RISC-V Verilog Processor

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/questa		simulation/questa
.gitattributes		.gitattributes
ALU.sv		ALU.sv
ALU.sv.bak		ALU.sv.bak
ControlUnit.sv		ControlUnit.sv
InstructionMemory.sv		InstructionMemory.sv
InstructionMemory.sv.bak		InstructionMemory.sv.bak
ProgramCounter.sv		ProgramCounter.sv
RegisterUnit.sv		RegisterUnit.sv
RegisterUnit.sv.bak		RegisterUnit.sv.bak
c5_pin_model_dump.txt		c5_pin_model_dump.txt
hexa.sv		hexa.sv
processor.qpf		processor.qpf
processor.qsf		processor.qsf
processor.qws		processor.qws
processor.sv		processor.sv
processor.sv.bak		processor.sv.bak

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