integrate agile hardware library components (#44)

* integrate agile hardware library components * hardware documentation on sphinx enable hw cw formatting verilog formatting fixed deps fixed arith renaming python3 for test hw script add images images from links
DeepWok · Feb 1, 2024 · 6a7f1cd · 6a7f1cd
1 parent ba50d8e
commit 6a7f1cd
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diff --git a/.github/workflows/testHardware.yml b/.github/workflows/testHardware.yml
@@ -4,11 +4,11 @@ on:
   push:
     branches: [ "main", "extended-tests" ]
     paths:
-      - 'mase_components/**'
+      - 'machop/mase_components/**'
   pull_request:
     branches: [ "main", "extended-tests" ]
     paths:
-      - 'mase_components/**'
+      - 'machop/mase_components/**'
   workflow_dispatch:
     logLevel:
           description: 'Log level'

diff --git a/.gitignore b/.gitignore
@@ -135,7 +135,6 @@ venv.bak/
 
 # mypy
 .mypy_cache/
-*.png
 
 # vscode
 .vscode

diff --git a/machop/chop/passes/graph/analysis/add_metadata/add_hardware_metadata.py b/machop/chop/passes/graph/analysis/add_metadata/add_hardware_metadata.py
@@ -237,13 +237,13 @@ def add_hardware_metadata_analysis_pass(graph, pass_args=None):
                 "device_id": -1,
                 "dependence_files": [
                     "cast/fixed_cast.sv",
-                    "fixed_arith/fixed_dot_product.sv",
-                    "fixed_arith/fixed_vector_mult.sv",
-                    "fixed_arith/register_slice.sv",
-                    "fixed_arith/fixed_accumulator.sv",
-                    "fixed_arith/fixed_adder_tree.sv",
-                    "fixed_arith/fixed_adder_tree_layer.sv",
-                    "fixed_arith/fixed_mult.sv",
+                    "fixed_arithmetic/fixed_dot_product.sv",
+                    "fixed_arithmetic/fixed_vector_mult.sv",
+                    "fixed_arithmetic/register_slice.sv",
+                    "fixed_arithmetic/fixed_accumulator.sv",
+                    "fixed_arithmetic/fixed_adder_tree.sv",
+                    "fixed_arithmetic/fixed_adder_tree_layer.sv",
+                    "fixed_arithmetic/fixed_mult.sv",
                     "common/join2.sv",
                     "linear/fixed_linear.sv",
                 ],

diff --git a/machop/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py b/machop/chop/passes/graph/analysis/add_metadata/hardware_metadata_layers.py
@@ -6,12 +6,12 @@
             "name": "fixed_linear",
             "dependence_files": [
                 "cast/rtl/fixed_cast.sv",
-                "fixed_arith/rtl/fixed_dot_product.sv",
-                "fixed_arith/rtl/fixed_vector_mult.sv",
-                "fixed_arith/rtl/fixed_accumulator.sv",
-                "fixed_arith/rtl/fixed_adder_tree.sv",
-                "fixed_arith/rtl/fixed_adder_tree_layer.sv",
-                "fixed_arith/rtl/fixed_mult.sv",
+                "fixed_arithmetic/rtl/fixed_dot_product.sv",
+                "fixed_arithmetic/rtl/fixed_vector_mult.sv",
+                "fixed_arithmetic/rtl/fixed_accumulator.sv",
+                "fixed_arithmetic/rtl/fixed_adder_tree.sv",
+                "fixed_arithmetic/rtl/fixed_adder_tree_layer.sv",
+                "fixed_arithmetic/rtl/fixed_mult.sv",
                 "common/rtl/register_slice.sv",
                 "common/rtl/join2.sv",
                 "common/rtl/skid_buffer.sv",

diff --git a/machop/chop/passes/graph/transforms/verilog/internal_file_dependences.py b/machop/chop/passes/graph/transforms/verilog/internal_file_dependences.py
@@ -2,12 +2,12 @@
     "linear": [
         "cast/rtl/fixed_cast.sv",
         "linear/rtl/fixed_linear.sv",
-        "fixed_arith/rtl/fixed_dot_product.sv",
-        "fixed_arith/rtl/fixed_accumulator.sv",
-        "fixed_arith/rtl/fixed_vector_mult.sv",
-        "fixed_arith/rtl/fixed_adder_tree.sv",
-        "fixed_arith/rtl/fixed_adder_tree_layer.sv",
-        "fixed_arith/rtl/fixed_mult.sv",
+        "fixed_arithmetic/rtl/fixed_dot_product.sv",
+        "fixed_arithmetic/rtl/fixed_accumulator.sv",
+        "fixed_arithmetic/rtl/fixed_vector_mult.sv",
+        "fixed_arithmetic/rtl/fixed_adder_tree.sv",
+        "fixed_arithmetic/rtl/fixed_adder_tree_layer.sv",
+        "fixed_arithmetic/rtl/fixed_mult.sv",
         "common/rtl/register_slice.sv",
         "common/rtl/skid_buffer.sv",
         "common/rtl/join2.sv",

diff --git a/machop/mase_components/ViT/test/affine_layernorm_tb.py b/machop/mase_components/ViT/test/affine_layernorm_tb.py
@@ -267,8 +267,8 @@ def runner():
         "../../../../components/ViT/affine_layernorm.sv",
         "../../../../components/cast/fixed_rounding.sv",
         "../../../../components/common/join2.sv",
-        "../../../../components/fixed_arith/fixed_vector_mult.sv",
-        "../../../../components/fixed_arith/fixed_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_vector_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_mult.sv",
         "../../../../components/common/fifo.sv",
     ]
     test_case = VerificationCase()

diff --git a/machop/mase_components/ViT/test/fixed_block_tb.py b/machop/mase_components/ViT/test/fixed_block_tb.py
@@ -1112,13 +1112,13 @@ def runner():
         "../../../../components/linear/fixed_2d_linear.sv",
         "../../../../components/cast/fixed_rounding.sv",
         "../../../../components/activations/fixed_relu.sv",
-        "../../../../components/fixed_arith/fixed_matmul_core.sv",
-        "../../../../components/fixed_arith/fixed_dot_product.sv",
-        "../../../../components/fixed_arith/fixed_accumulator.sv",
-        "../../../../components/fixed_arith/fixed_vector_mult.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree_layer.sv",
-        "../../../../components/fixed_arith/fixed_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_matmul_core.sv",
+        "../../../../components/fixed_arithmetic/fixed_dot_product.sv",
+        "../../../../components/fixed_arithmetic/fixed_accumulator.sv",
+        "../../../../components/fixed_arithmetic/fixed_vector_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree_layer.sv",
+        "../../../../components/fixed_arithmetic/fixed_mult.sv",
     ]
     test_case = VerificationCase()
 

diff --git a/machop/mase_components/ViT/test/fixed_mlp_tb.py b/machop/mase_components/ViT/test/fixed_mlp_tb.py
@@ -448,13 +448,13 @@ def runner():
         "../../../../components/linear/fixed_linear.sv",
         "../../../../components/cast/fixed_rounding.sv",
         "../../../../components/activations/fixed_relu.sv",
-        "../../../../components/fixed_arith/fixed_matmul_core.sv",
-        "../../../../components/fixed_arith/fixed_dot_product.sv",
-        "../../../../components/fixed_arith/fixed_accumulator.sv",
-        "../../../../components/fixed_arith/fixed_vector_mult.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree_layer.sv",
-        "../../../../components/fixed_arith/fixed_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_matmul_core.sv",
+        "../../../../components/fixed_arithmetic/fixed_dot_product.sv",
+        "../../../../components/fixed_arithmetic/fixed_accumulator.sv",
+        "../../../../components/fixed_arithmetic/fixed_vector_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree_layer.sv",
+        "../../../../components/fixed_arithmetic/fixed_mult.sv",
     ]
     test_case = VerificationCase()
 

diff --git a/machop/mase_components/ViT/test/fixed_pvt_tb.py b/machop/mase_components/ViT/test/fixed_pvt_tb.py
@@ -1490,13 +1490,13 @@ def runner():
         "../../../../components/common/unpacked_skid_buffer.sv",
         "../../../../components/common/join2.sv",
         "../../../../components/common/split2.sv",
-        "../../../../components/fixed_arith/fixed_matmul_core.sv",
-        "../../../../components/fixed_arith/fixed_dot_product.sv",
-        "../../../../components/fixed_arith/fixed_accumulator.sv",
-        "../../../../components/fixed_arith/fixed_vector_mult.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree_layer.sv",
-        "../../../../components/fixed_arith/fixed_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_matmul_core.sv",
+        "../../../../components/fixed_arithmetic/fixed_dot_product.sv",
+        "../../../../components/fixed_arithmetic/fixed_accumulator.sv",
+        "../../../../components/fixed_arithmetic/fixed_vector_mult.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree_layer.sv",
+        "../../../../components/fixed_arithmetic/fixed_mult.sv",
     ]
     test_case = VerificationCase()
 

diff --git a/machop/mase_components/ViT/test/hash_softmax_tb.py b/machop/mase_components/ViT/test/hash_softmax_tb.py
@@ -265,9 +265,9 @@ def runner():
     verilog_sources = [
         "../../../../components/ViT/hash_softmax.sv",
         "../../../../components/conv/roller.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree.sv",
-        "../../../../components/fixed_arith/fixed_adder_tree_layer.sv",
-        "../../../../components/fixed_arith/fixed_accumulator.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree.sv",
+        "../../../../components/fixed_arithmetic/fixed_adder_tree_layer.sv",
+        "../../../../components/fixed_arithmetic/fixed_accumulator.sv",
         "../../../../components/common/join2.sv",
         "../../../../components/common/split2.sv",
         "../../../../components/common/fifo.sv",

diff --git a/...p/mase_components/fixed_arith/__init__.py → ...op/mase_components/arithmetic/__init__.py b/...p/mase_components/fixed_arith/__init__.py → ...op/mase_components/arithmetic/__init__.py
diff --git a/...se_components/fixed_arith/rtl/__init__.py → ...ase_components/arithmetic/rtl/__init__.py b/...se_components/fixed_arith/rtl/__init__.py → ...ase_components/arithmetic/rtl/__init__.py
diff --git a/machop/mase_components/arithmetic/rtl/mac.sv b/machop/mase_components/arithmetic/rtl/mac.sv
@@ -0,0 +1,77 @@
+
+module mac #(
+    parameter PRECISION   = top_pkg::FLOAT_32,
+    parameter FLOAT_WIDTH = 32,
+    parameter DATA_WIDTH  = 32
+) (
+    input logic core_clk,
+    input logic resetn,
+
+    input  logic in_valid,
+    output logic in_ready,
+
+    input logic [DATA_WIDTH-1:0] a,
+    input logic [DATA_WIDTH-1:0] b,
+
+    output logic [DATA_WIDTH-1:0] accumulator,
+
+    input logic                  overwrite,
+    input logic [DATA_WIDTH-1:0] overwrite_data
+
+);
+
+  if (PRECISION == top_pkg::FLOAT_32) begin
+
+    float_mac #(
+        .FLOAT_WIDTH(FLOAT_WIDTH)
+    ) float_mac_i (
+        .core_clk,
+        .resetn,
+
+        .in_valid,
+        .in_ready,
+
+        .a,
+        .b,
+
+        .overwrite,
+        .overwrite_data,
+
+        .accumulator
+    );
+
+  end else begin
+
+    fixed_point_mac #(
+        .DATA_WIDTH(DATA_WIDTH)
+    ) fixed_point_mac_i (
+        .core_clk,
+        .resetn,
+
+        .in_valid,
+        .in_ready,
+
+        .a,
+        .b,
+
+        .overwrite,
+        .overwrite_data,
+
+        .accumulator
+    );
+
+  end
+
+  // ======================================================================================================
+  // Assertions
+  // ======================================================================================================
+
+  P_acc_constant :
+  cover property (
+    @(posedge core_clk) disable iff (!resetn)
+    (in_valid && in_ready) |=> (accumulator == $past(
+      accumulator, 1
+  )));
+
+endmodule
+
diff --git a/...e_components/fixed_arith/test/__init__.py → ...se_components/arithmetic/test/__init__.py b/...e_components/fixed_arith/test/__init__.py → ...se_components/arithmetic/test/__init__.py
diff --git a/machop/mase_components/axi/__init__.py b/machop/mase_components/axi/__init__.py
diff --git a/machop/mase_components/axi/rtl/__init__.py b/machop/mase_components/axi/rtl/__init__.py