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1. Multiplexer-Simulation-in-Vivado Multiplexer-Simulation-in-Vivado Public

   Forked from TharunPR/Multiplexer-Simulation-in-Vivado

   In this experiment, a 4:1 Multiplexer (MUX) is designed and simulated using Verilog HDL in various modeling styles: Gate-Level, Data Flow, Behavioral, and Structural.

2. Seven-segment-display-using-Verilog-HDL- Seven-segment-display-using-Verilog-HDL- Public

   Forked from Naveen272006/Seven-segment-display-using-Verilog-HDL-

   To design and simulate a seven-segment display driver using Verilog HDL, and verify its functionality through a testbench in the Vivado 2023.1 environment.

3. SIMULATION-AND-IMPLEMENTATION-OF-MULTIPLEXER SIMULATION-AND-IMPLEMENTATION-OF-MULTIPLEXER Public

4. Ideal-Sampling Ideal-Sampling Public

   Forked from DrBalaKumarD/Ideal-Sampling

5. Natural-sampling Natural-sampling Public

   Forked from DrBalaKumarD/Natural-sampling

6. Pulse-Code-Modulation Pulse-Code-Modulation Public

   Forked from DrBalaKumarD/Pulse-Code-Modulation