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1. AjitesshR-RISC-V-Chip-Tapeout-Program_VSD AjitesshR-RISC-V-Chip-Tapeout-Program_VSD Public

   This repository is to document my progress in VSD's RISC-V Chip Tapeout program. Let's see how consistent I am in this journey.

2. AjitesshR-RISC-V-Chip-Tapeout-Program_VSD-week-2 AjitesshR-RISC-V-Chip-Tapeout-Program_VSD-week-2 Public

   This is week 1 repository which documents my journey through **VSD's RISC-V Chip Tapeout Program** - from RTL design to physical implementation. Follow along as we explore the complete chip design …