This project decodes 433.920 MHz RF signals from wireless remotes in real-time using Verilog on a Nexys A7 FPGA.
The RF pulse train is captured by a receiver module and decoded by a finite state machine (FSM), then output over UART to a terminal.
Planned stretch goal: Add OLED display output using SSD1306 module via I2C.
This project uses a Nexys A7 FPGA to decode 433.920 MHz wireless remote signals in real-time.
A simple RF receiver module (RXB6) captures the pulses, which are processed by a Verilog finite state machine.
Decoded data is sent to a PC over UART and displayed live in a terminal window (PuTTY).
- Remote Control sends OOK (on-off keying) pulses at 433 MHz.
- RXB6 Module picks up the RF pulses.
- Nexys A7 FPGA measures pulse widths and decodes them with a custom FSM.
- Verilog FSM Decoder detects pulse width timing and converts it to binary data.
- UART Transmitter sends decoded bits to a PC terminal over USB.
- PC Terminal (PuTTY) displays decoded packets live on the computer screen.
| Folder | Purpose |
|---|---|
/src |
Verilog source code (FSM, UART, top-level module) |
/doc |
Timing diagrams, system diagrams, protocol notes |
/captures |
SDR# screenshots and signal captures |
/images |
Terminal output, hardware setup photos |
/testbench |
Simulation files (to be added) |
/xdc |
Vivado constraint files for FPGA pin mapping |
- RTL-SDR capture working ✅
- RXB6 module testing in progress 🛠️
- FSM design started 🛠️
- UART output module in planning phase 🛠️
- Build a working pulse-width decoding FSM.
- Output decoded packets via UART to PC.
- (Stretch Goal) Display decoded data on an OLED screen.
I wanted a hands-on way to practice both RF signal processing and FPGA design.
This project combines radio protocol analysis, real-time signal decoding, Verilog development, and embedded system communication — all in one pipeline.
MIT