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Maven Silicon Pvt Ltd
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Router_verification
Router_verification PublicRouter 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-…
SystemVerilog 3
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AHB_APB_VERIFICATION
AHB_APB_VERIFICATION Public1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE…
Verilog 2
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-100--days--coding--challenge
-100--days--coding--challenge Publicin this repo will continue with rtl codesfor implementation od various design using verilog in xilinx ISE 14.7 and modelsim and digital compiler.
Verilog 2
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Router_1_3
Router_1_3 PublicRouter 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-…
Verilog 1
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Counter_verification
Counter_verification Public1)Architected the class based verification environment in UVM. 2)Defined Verification Plan. l 66% 3)Verified the RTL module with UVM Test Bench with different test scenarios like single READ,WRITE…
SystemVerilog 1
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100_days_verification_challenge
100_days_verification_challenge Publicin this repo will continue with rtl codes for implementation and verification of the designing, and 100 percentage of coverage model. various design using system verilog in questa and vcs and digit…
SystemVerilog 2
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