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Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
Router_architecture.pdf		Router_architecture.pdf
router_fifo.v		router_fifo.v
router_fifo_tb.v		router_fifo_tb.v
router_fsm.v		router_fsm.v
router_fsm_tb.v		router_fsm_tb.v
router_reg.v		router_reg.v
router_reg_tb.v		router_reg_tb.v
router_sync.v		router_sync.v
router_sync_tb.v		router_sync_tb.v
router_top.v		router_top.v
router_top_tb.v		router_top_tb.v