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Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦

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2 to 1 mux.PNG
2 to 1 mux.PNG
 
 
3 to 8.PNG
3 to 8.PNG
 
 
4 to 1 MUX.PNG
4 to 1 MUX.PNG
 
 
D Flip Flop.ms14
D Flip Flop.ms14
 
 
Exp Sampling.PNG
Exp Sampling.PNG
 
 
Exp1.PNG
Exp1.PNG
 
 
Exp10.PNG
Exp10.PNG
 
 
Exp11.PNG
Exp11.PNG
 
 
Exp12.PNG
Exp12.PNG
 
 
Exp13.PNG
Exp13.PNG
 
 
Exp14.PNG
Exp14.PNG
 
 
Exp2.PNG
Exp2.PNG
 
 
Exp3.PNG
Exp3.PNG
 
 
Exp4.PNG
Exp4.PNG
 
 
Exp5.PNG
Exp5.PNG
 
 
Exp6.PNG
Exp6.PNG
 
 
Exp7.PNG
Exp7.PNG
 
 
Exp8.PNG
Exp8.PNG
 
 
Exp9.PNG
Exp9.PNG
 
 
Final Exp Sampling'.PNG
Final Exp Sampling'.PNG
 
 
Full Adder using 3 to 8.PNG
Full Adder using 3 to 8.PNG
 
 
Full Adder using two half adders.PNG
Full Adder using two half adders.PNG
 
 
Full Adder.PNG
Full Adder.PNG
 
 
Gaurav_Singh_9915103252_F8_Experiment1_8_to_1_using_4_to_1_and_2_to_1.ms11
Gaurav_Singh_9915103252_F8_Experiment1_8_to_1_using_4_to_1_and_2_to_1.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_AND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_AND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_AND_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_AND_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_NOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_NOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_NOT.ms11
Gaurav_Singh_9915103252_F8_Experiment1_NOT.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_NOT_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_NOT_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_NOT_using_NOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_NOT_using_NOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_OR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_OR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_OR_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_OR_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_OR_using_NOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_OR_using_NOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_XNOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_XNOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_XNOR_using_NOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_XNOR_using_NOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_XOR.ms11
Gaurav_Singh_9915103252_F8_Experiment1_XOR.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment1_XOR_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment1_XOR_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Full_Adder.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Full_Adder.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Full_Adder_using_two_half_adder.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Full_Adder_using_two_half_adder.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Full_Substractor.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Full_Substractor.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Half_Adder.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Half_Adder.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Half_Adder_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Half_Adder_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Half_Substractor.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Half_Substractor.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment2_Half_Substractor_using_NAND.ms11
Gaurav_Singh_9915103252_F8_Experiment2_Half_Substractor_using_NAND.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment3_3_to_8_Decoder.ms11
Gaurav_Singh_9915103252_F8_Experiment3_3_to_8_Decoder.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment3_Full_adder_using_3_to_8_decoder.ms11
Gaurav_Singh_9915103252_F8_Experiment3_Full_adder_using_3_to_8_decoder.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment4_2_to_1_MUX.ms11
Gaurav_Singh_9915103252_F8_Experiment4_2_to_1_MUX.ms11
 
 
Gaurav_Singh_9915103252_F8_Experiment4_4_to_1_MUX.ms11
Gaurav_Singh_9915103252_F8_Experiment4_4_to_1_MUX.ms11
 
 
Half Adder.PNG
Half Adder.PNG
 
 
Half Substractor using Nand.PNG
Half Substractor using Nand.PNG
 
 
Half Substractor.PNG
Half Substractor.PNG
 
 
J K Flip Flop.PNG
J K Flip Flop.PNG
 
 
J K flip flop0.ms14
J K flip flop0.ms14
 
 
README.md
README.md
 
 
S R Flip Flop.PNG
S R Flip Flop.PNG
 
 
S R Flip flop.ms14
S R Flip flop.ms14
 
 
Sine_Discrete.m
Sine_Discrete.m
 
 
T Flip Flop.PNG
T Flip Flop.PNG
 
 
T flip flop.ms14
T flip flop.ms14
 
 
Thumbs.db
Thumbs.db
 
 
d Flip flop.PNG
d Flip flop.PNG
 
 
exp7.m
exp7.m
 
 
reconstructed sine.PNG
reconstructed sine.PNG
 
 
vlsi_7.PNG
vlsi_7.PNG
 
 

Repository files navigation

VLSI

Playing with logic gates, find my approach to make decison making cirucits.

  1. 2 to 1 mux
  2. 3 to 8
  3. 4 to 1 MUX
  4. D Flip Flop
  5. Full Adder using 3 to 8
  6. Full Adder using two half adders
  7. Full Adder
  8. 8_to_1_using_4_to_1_and_2_to_1
  9. AND
  10. AND_using_NAND
  11. NAND
  12. NOR
  13. NOT
  14. NOT_using_NAND
  15. NOT_using_NOR
  16. OR
  17. OR_using_NAND
  18. OR_using_NOR
  19. XNOR
  20. XNOR_using_NOR
  21. XOR
  22. XOR_using_NAND
  23. Full_Adder
  24. Full_Adder_using_two_half_adder
  25. Full_Substractor
  26. Half_Adder
  27. Half_Adder_using_NAND
  28. Half_Substractor
  29. Half_Substractor_using_NAND
  30. 3_to_8_Decoder
  31. Full_adder_using_3_to_8_decoder
  32. 2_to_1_MUX
  33. 4_to_1_MUX
  34. Half Adder
  35. Half Substractor using Nand
  36. Half Substractor
  37. J K Flip Flop
  38. S R Flip Flop
  39. Sine_Discrete
  40. T Flip Flop
  41. d Flip flop
  42. fcfs
  43. preemetive_sjfs
  44. preemitive_priority_scheduling
  45. priority_scheduling
  46. reconstructed sine
  47. sjfs
  48. thread

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Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦

Topics

logic-gates adder sine flip-flop half-adder electronics-engineering logical-programming full-adder decison-circuits

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