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64-bit back-end interface fails #241

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jjts opened this issue Nov 3, 2022 · 5 comments
Open

64-bit back-end interface fails #241

jjts opened this issue Nov 3, 2022 · 5 comments

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@jjts
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jjts commented Nov 3, 2022

This was reported by Salima

a test case should be created

if the problem exists it should be fixed

can the axi ram we have been using support 64-bits?

@jjts
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jjts commented Nov 3, 2022

related to iob-soc #433

@jjts
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jjts commented Nov 19, 2022

A CPU trap issue occurs when the backend data width is set to 64 instead of 32, when cache is in iob-soc

iob-soc issue iob-soc #433 has been closed

@spzeno
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spzeno commented Mar 8, 2023

Hi,I've fonud a testcase you mentioned above:

the iob-cache's parameter set is:
image
image

It's backend is 64 bit AXI interface and it is connected with a AXI-bus-matrix's master port.
A 64 bit memory with AXI interface is connected with AXI-bus-matrix's slave port.

if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

then no fail msg uart will put.

However, if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
*(volatile int *)(0xf0090000) = 0x3;
*(volatile int *)(0xf0098000) = 0x4;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

error will happen:
image

the waveform:
image

I think that the errors may because of these signals
image

EDIT: I found that if I set cache's N_WAYS to 1, there will be no error

@jjts
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jjts commented Mar 9, 2023

Hi @spzeno , pls try branch fix#241 and let me know if it fixes the issue

@spzeno
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spzeno commented Mar 10, 2023

Oops,seems like it failed as soon as the first time try to write
image

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