VerilogModules

This repository contains a collection of Verilog modules designed for educational and practical applications in digital design. The modules were developed and tested using Intel Quartus and ModelSim on a Delite FPGA MAX 10, as part of a project in collaboration with Intel.

Modules

Here is a list of the available Verilog modules in this repository:

• ClockDivider: A module that divides the input clock frequency to a lower frequency.
• Debouncer: A module used to eliminate noise from mechanical switches.
• Decoder4digits: A module designed to decode binary inputs into four-digit outputs.
• Decoder7seg: A module that decodes 4-bit binary numbers into 7-segment display outputs.
• Gates: Basic logic gate implementations.
• MaquinaEstado_simple (Simple State Machine): A simple implementation of a state machine.
• Multiplexor: A module that selects one of many input signals and forwards the selected input into a single line.
• PWM (Pulse Width Modulation): A module for generating a pulse-width modulated signal.
• PrimeNumbers: A module designed to identify prime numbers.
• TopModuleCounter_clockDivider: A top module that integrates a counter with a clock divider.

Prerequisites

• Intel Quartus Prime
• ModelSim
• Delite FPGA MAX 10 board

Installation

To use these modules, clone this repository to your local machine using the following command:

git clone https://github.com/Ineso1/VerilogModules.git

Usage

Each module is placed in its respective folder. Navigate to the desired module's directory, and you will find the Verilog source files along with a README.md file explaining how to use the module, its purpose, and any additional information.

To compile and simulate any of these modules, follow the standard process in Intel Quartus and ModelSim:

1. Open the project in Intel Quartus.
2. Compile the design.
3. Simulate the design in ModelSim.