A RISC-V CPU Core of Base RV32I ISA implemented in TL-Verilog. The current implementation consists of 31 instructions out of the 47 in the Base RV32I ISA, all the instructions which can independently run on the CPU have been implemented.
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A RISC-V CPU Core of Base RV32I ISA implemented in TL-Verilog.
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JagratPatkar/RISC-V
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A RISC-V CPU Core of Base RV32I ISA implemented in TL-Verilog.
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