Skip to content

A RISC-V simulator, which can simulate the Base RV32I ISA

License

Notifications You must be signed in to change notification settings

JagratPatkar/RSIM

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

26 Commits
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

RSIM

A RISC-V simulator, which can simulate the Base RV32I ISA. The simulator takes a .bin file as input, created from the RASM assembler.

Supported Instructions

R Type: ADD, SUB, SIL, SLT, SLTU, XOR, SRL, SRA, OR, AND

I Type: ADDI, JALR, SLLI, SLTI, SLTIU, XORI, SRLI, SRAI, ORI, ANDI, LW, LH, LB

S Type: SB, SH, SW

B Type: BEQ, BNE, BLT, BGE, BLTU, BGEU

J Type: JAL

U Type: LUI, AUIPC

About

A RISC-V simulator, which can simulate the Base RV32I ISA

Topics

Resources

License

Stars

Watchers

Forks

Languages