Xilinx tools not correctly implementing asynchronous FIFO.

[drichmond]

This causes a missing first-dword in about 1-in-10 transfers.

Does not seem to affect Altera (unlikely it's a logic bug in our code)

[cjmraziii]

What was the resolution of this issue?

[drichmond]

Wasn't Xilinx specific. In the end, the state machine in tx_port_monitor had a bug in it, that was caused by an earlier fix on a related issue.

Why do you ask?

[cjmraziii]

I am seeing an issue that sounds similar where sometimes the 1st two DWORDS are coming through wrong. It seems to be much less prevalent using the user_clk output of the RIFFA module vs my internal 100MHz asynchronous clock. Was the issue resolved in 2.2.2?

[drichmond]

Yes

On Nov 18, 2016, at 11:11 AM, cjmraziii notifications@github.com wrote:

I am seeing an issue that sounds similar where sometimes the 1st two DWORDS are coming through wrong. It seems to be much less prevalent using the user_clk output of the RIFFA module vs my internal 100MHz asynchronous clock. Was the issue resolved in 2.2.2?

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