LL_contest

Low Power project for Synthesis and Optimization of Digital Systems. Optimization procedure for (Area, Delay, Power) with DualVth std_cells design, to be used within PrimeTime.

SETUP (WORK_SYNTHESIS environment)

PrimeTime synthesis script
Should go: ~/WORK_SYNTHESIS/scripts
Dependences: power_features.tcl, synopsys_pt.setup

DC compiler synthesis script
Should go: ~/WORK_SYNTHESIS/scripts
Dependences: power_features.tcl, synopsys_dc.setup

DC setup script
Should go: ~/WORK_SYNTHESIS/tech/STcmos65/

PT setup script
Should go: ~/WORK_SYNTHESIS/tech/STcmos65/

DualVth enable script Should go: ~/WORK_SYNTHESIS/scripts

RTL (combinatorial)

Sythesis scripts are working on C1908 netlist, change block name attribute inside pt_analysis.tcl and synthesis.tcl if y want to test another netlist.

c432 struct
c1908 struct
c5315 struct
Should go: ~/WORK_SYNTHESIS/rtl

main script
report