- ๐ B.Tech student at IIT Indore
- ๐ก Passionate about VLSI, digital design, and microarchitecture
- ๐ป Comfortable with C++ and Data Structures & Algorithms
- ๐ Learning Python to automate and enhance my workflow
- Languages: Verilog, C++, Python
- Domains: Digital Logic, Pipelining, FPGA, DSA
- Tools: Vivado, LTSpice, GitHub, VS Code
- VLSI & ASIC Design
- CPU Microarchitecture
- Hardware-Software Co-Design
- ๐ง Email: ee240002036@iiti.ac.in
- ๐ผ LinkedIn: https://www.linkedin.com/in/manthan-gupta-88164a32a/
โFrom gates to graphs โ building systems and solving problems.โ