Introducing a Visual Programming language for Verilog (HDL) built on top of Google's Blockly API using Vanilla JavaScript.
First clone the repository, since it is built with Vanilla JavaScript thus no dependecies or libraries will be required. Navigate to the project root directory and open "index.html" file, Now your default browser will open redirecting you to a page where our Visual platform exists.
Verilog is a Hardware descriptive language; a textual format to describe electronic systems and circuits. Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis. Verilog is an HDL; however, VHDL is a totally different, they both share some fundumentals of being both a Hardware descriptive languages but both are different. Our main aspect of the project is Verilog and soothing the design procedure.
Field Programmable Gate array or FPGA as some hardware developers might relate to, is an integrated circuit which gives the developer the power to be configured on his/her needs after manufacturing - hence, the term field-programmable. This powerful integrated circuit comes in different sizes and by different manufacturers. Verilog is very efficient tool for implementing ideas with FPGA also it shares some aspects of a regular programming language such as Java or C but with combining in features of Hardware logic which makes it a little hard to learn for beginners since it include rigid syntax and different semantics compared with other programming languages also the user must have a basic knowledge about computer hardware.
Visual Verilog is an approach used to soothe the process of learning Verilog also offering automated features instead of the developer to model it himself which requires time and effort. Visual Verilog is a Visual language introduced by the author: Marwan Sami Youssef built upon Google's Blockly API which is a JavaScript library, Blockly is Visual Programming Language. For people with minimal knowledge of Visual Languages; an approach to describe elements graphically rather than specifiying them textually which makes the learning process much easier.
After following up with the Getting started tips. Currently the user should be looking at my platform workspace where on the left there is a panel of categories, on the very top one will find buttons each with different functionality as indicated on the button's labels and finally in the middle is our workspace. The panel of categories contains blocks each unique with different purpose of use, strucute to give the designer the freedom of creation. These blocks combine together at the end to generate valid Verilog modules, testbenches or even lines of code. The user could test his/her output using another open source simulation platform which allows users to grab their generated Verilog code and plug it in the simulator to check for results, errors or even waveforms.
Many newbie users would get lost using the blocks in the correct sequence, thus I have created a documentation page to guide users into how to use the platform and even reduce the possibility of Generating code with no function. Please take a dive deeper into the Visual Verilog documentation provided. Users could access the documentation web page by going into index.html page and then click on the third button which will redirect the users to the Documentation.