GitHub - Mayank-Parasar/verilog_code: Contains sample verilog (HDL) code

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
.gitignore		.gitignore
adder_explicit.v		adder_explicit.v
adder_hier.v		adder_hier.v
adder_implicit.v		adder_implicit.v
and_gat_tb.v		and_gat_tb.v
and_gate.v		and_gate.v
ansiport_example.v		ansiport_example.v
cntr		cntr
comma_edge.v		comma_edge.v
comment.v		comment.v
counter.v		counter.v
counter.vcd		counter.vcd
counter_tb.v		counter_tb.v
dff.v		dff.v
explicit.v		explicit.v
fileIO.v		fileIO.v
force_release.v		force_release.v
fork_join.v		fork_join.v
gates.v		gates.v
gen_up_dn_cntr.v		gen_up_dn_cntr.v
gen_up_dn_cntr.vcd		gen_up_dn_cntr.vcd
gen_up_dn_cntr_tb		gen_up_dn_cntr_tb
gen_up_dn_cntr_tb.v		gen_up_dn_cntr_tb.v
generate_example.v		generate_example.v
hello_world.v		hello_world.v
implicit.v		implicit.v
input.txt		input.txt
mid-term-Q1.v		mid-term-Q1.v
mid-term-Q1_tb.v		mid-term-Q1_tb.v
monitor.txt		monitor.txt
mux_from_gates.v		mux_from_gates.v
myFIFO.v		myFIFO.v
myFIFO_1.v		myFIFO_1.v
myFIFO_tb		myFIFO_tb
myFIFO_tb.v		myFIFO_tb.v
myfifo.vcd		myfifo.vcd
operator.v		operator.v
parity.v		parity.v
pri_encoder_using_if.v		pri_encoder_using_if.v
sample.txt		sample.txt
signed_number		signed_number
signed_number.v		signed_number.v
syn_fifo.v		syn_fifo.v
syn_fifo1.v		syn_fifo1.v
udp_body.v		udp_body.v
udp_body_tb.v		udp_body_tb.v
up_dn_cntr.v		up_dn_cntr.v