sys: handle the interlace and timeout for new resolution.

SNES.sv

@@ -28,7 +28,7 @@ module emu
 	input         RESET,
 
 	//Must be passed to hps_io module
-	inout  [44:0] HPS_BUS,
+	inout  [45:0] HPS_BUS,
 
 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
@@ -433,14 +433,11 @@ wire gg_available;
 // Integer values are in BIG endian byte order, so it up to the loader
 // or generator of the code to re-arrange them correctly.
 
-// SNES files come in with 512 extra words of data at the start
-wire [24:0] code_addr = ioctl_addr - 10'd512;
-
 always_ff @(posedge clk_sys) begin
-	gg_code[128] <= 1'b0;
+	gg_code[128] <= 0;
 
 	if (code_download & ioctl_wr) begin
-		case (code_addr[3:0])
+		case (ioctl_addr[3:0])
 			0:  gg_code[111:96]  <= ioctl_dout; // Flags Bottom Word
 			2:  gg_code[127:112] <= ioctl_dout; // Flags Top Word
 			4:  gg_code[79:64]   <= ioctl_dout; // Address Bottom Word
@@ -449,8 +446,8 @@ always_ff @(posedge clk_sys) begin
 			10: gg_code[63:48]   <= ioctl_dout; // Compare top Word
 			12: gg_code[15:0]    <= ioctl_dout; // Replace Bottom Word
 			14: begin
-				gg_code[31:16]   <= ioctl_dout; // Replace Top Word
-				gg_code[128]     <=  1'b1;      // Clock it in
+				gg_code[31:16]    <= ioctl_dout; // Replace Top Word
+				gg_code[128]      <= 1;          // Clock it in
 			end
 		endcase
 	end

sys/hps_io.v

@@ -33,7 +33,7 @@
 module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
 (
 	input             clk_sys,
-	inout      [44:0] HPS_BUS,
+	inout      [45:0] HPS_BUS,
 
 	// parameter STRLEN and the actual length of conf_str have to match
 	input [(8*STRLEN)-1:0] conf_str,
@@ -174,15 +174,18 @@ wire de      = HPS_BUS[40];
 wire hs      = HPS_BUS[39];
 wire vs      = HPS_BUS[38];
 wire vs_hdmi = HPS_BUS[44];
+wire f1      = HPS_BUS[45];
 
 reg [31:0] vid_hcnt = 0;
 reg [31:0] vid_vcnt = 0;
 reg  [7:0] vid_nres = 0;
+reg  [1:0] vid_int  = 0;
 integer hcnt;
 
 always @(posedge clk_vid) begin
 	integer vcnt;
 	reg old_vs= 0, old_de = 0, old_vmode = 0;
+	reg [3:0] resto = 0;
 	reg calch = 0;
 
 	if(ce_pix) begin
@@ -194,15 +197,22 @@ always @(posedge clk_vid) begin
 		if(old_de & ~de) calch <= 0;
 
 		if(old_vs & ~vs) begin
-			if(hcnt && vcnt) begin
-				old_vmode <= new_vmode;
-				if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
-				vid_hcnt <= hcnt;
-				vid_vcnt <= vcnt;
+			vid_int <= {vid_int[0],f1};
+			if(~f1) begin
+				if(hcnt && vcnt) begin
+					old_vmode <= new_vmode;
+
+					//report new resolution after timeout
+					if(resto) resto <= resto + 1'd1;
+					if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
+					if(&resto) vid_nres <= vid_nres + 1'd1;
+					vid_hcnt <= hcnt;
+					vid_vcnt <= vcnt;
+				end
+				vcnt <= 0;
+				hcnt <= 0;
+				calch <= 1;
 			end
-			vcnt <= 0;
-			hcnt <= 0;
-			calch <= 1;
 		end
 	end
 end
@@ -433,7 +443,7 @@ always@(posedge clk_sys) begin
 
 					//Video res.
 					'h23: case(byte_cnt)
-								1: io_dout <= vid_nres;
+								1: io_dout <= {|vid_int, vid_nres};
 								2: io_dout <= vid_hcnt[15:0];
 								3: io_dout <= vid_hcnt[31:16];
 								4: io_dout <= vid_vcnt[15:0];

sys/sys_top.v

@@ -842,7 +842,7 @@ emu emu
 (
 	.CLK_50M(FPGA_CLK3_50),
 	.RESET(reset),
-	.HPS_BUS({HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
+	.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
 
 	.CLK_VIDEO(clk_vid),
 	.CE_PIXEL(ce_pix),