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Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,7 @@ This Arm processor implements the Arm v8 instructions set.
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This Arm processor implements the Arm v8 extra cryptographic instructions (i.e. AES, SHA1 and SHA2).
This Arm processor implements the Arm v8 extra cryptographic instructions (for example, AES, SHA1 and SHA2).
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Expand All @@ -461,18 +461,40 @@ This Arm processor implements the Arm v8 extra CRC32 instructions.
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This Arm processor implements the Arm v8.1 atomic instructions (e.g. CAS, SWP).
This Arm processor implements the Arm v8.1 atomic instructions (for example, CAS, SWP).
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<tr>
<td width="40%"><a id="PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE"></a><a id="pf_arm_v82_dp_instructions_available"></a><dl>
<dt><b>PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE</b></dt>
<dt>43</dt>
</dl>
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<td width="60%">
This Arm processor implements the Arm v8.2 DP instructions (for example, SDOT, UDOT). This feature is optional in Arm v8.2 implementations and mandatory in Arm v8.4 implementations.
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<tr>
<td width="40%"><a id="PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE"></a><a id="pf_arm_v83_jscvt_instructions_available"></a><dl>
<dt><b>PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE</b></dt>
<dt>44</dt>
</dl>
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<td width="60%">
This Arm processor implements the Arm v8.3 JSCVT instructions (for example, FJCVTZS).
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<tr>
<tr>
<td width="40%"><a id="PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE"></a><a id="pf_arm_v83_lrcpc_instructions_available"></a><dl>
<dt><b>PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE</b></dt>
<dt>34</dt>
<dt>45</dt>
</dl>
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<td width="60%">
This Arm processor implements the Arm v8.3 LRCPC instructions (e.g. ldapr). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
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