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1. RV32_SoC_Design RV32_SoC_Design Public

   The objective of this project is to design, verify, and implement a RISC-V-based System-on-Chip (SoC) (baseline version), featuring a 6-stage pipelined processor supporting the RV32I instruction set.

   Verilog 2

2. Lab7_DSD Lab7_DSD Public

   Source Codes for the tasks of Lab 7: Finite State Machines

   Tcl 1

3. Lab3_C Lab3_C Public

   This git repository includes the code for tasks 1 - 7 of Lab 3: Iterative Algorithms, Support for Iterative Algorithms through C Loops, Real-World Applications - Problem Solving Skills using C..

   C

4. Lab4_C Lab4_C Public

   Source codes for tasks 1 - 6 of Lab 4: Nested Loops and Intro to Arrays - Problem Solving Skills using C

   C

5. Lab5_C Lab5_C Public

   Source codes for tasks 1 - 5 of Lab 5: Pointers and Functions - Problem Solving Skills using C

   C

6. Lab6_C Lab6_C Public

   Source codes for tasks 1 - 5 of Lab 6: Pointers, Dynamic Memory Allocation and their Applications - Problem Solving Skills using C

   C