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MIT-licensed Goldilocks batch inversion and division hardware accelerator. Chisel source and generated SystemVerilog.
Released design
| Item | Scope |
|---|---|
| Computation | Montgomery-style batch inversion and elementwise numerator/denominator division |
| Field | Goldilocks p = 2^64 - 2^32 + 1; canonical 64-bit elements |
| Bundled configuration | 16 interleaved scan contexts, maximum batch length 65,536; top GoldilocksBatchInversion |
| Native boundary | Task, ordered numerator/denominator stream, indexed value/zero flag and completion |
| Task overlap | At most two tasks outstanding; complete input batches are not interleaved |
Engineering evidence and integration
Project overview · Native interface · Reproduction · Performance · Synthesis scope · License
Recorded verification scope: Independent C and Python references check every vector before RTL tests. Generated and bundled SV each run eight documented categories: ideal inversion/division, varied lengths and zero denominators with stalls, reset, a deliberate reference error, malformed tasks, and isolated inversion/division. The maximum-length-32 command is a quick installation check, not a substitute for the released 65,536-element configuration.
Integration boundary: Zero denominators produce value zero and a per-element zero flag, with ZERO_DENOMINATOR completion rather than ordinary SUCCESS. Empty batches, BAD_PARAM and BAD_FRAME have distinct behavior. Tags must distinguish outstanding tasks; supply each batch in order and wait for real completion. The 16 contexts are a hardware scheduling choice, not 16 independent external request lanes. This unit does not implement proof relations or BN254 arithmetic.
Evidence applies to the documented version, configuration and target. Simulation, synthesis and board/silicon measurements are distinct. These are standalone compute blocks, not an end-to-end zero-knowledge prover.
Custom integration and licensing
For optional custom ASIC/FPGA accelerator development and integration, visit OpenRTL Lab. MIT-licensed commercial use does not require a paid engagement. Retain applicable copyright, license and third-party notices.
Release downloads
These downloads provide hardware sources and bundled RTL for this version. Archive annotations and documentation can differ from the online source tree; use the product file list for integration and the linked documents for verification scope.
OpenRTL organization · ZK accelerator catalogue
简体中文
MIT 开源 Goldilocks 批量求逆与除法硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
已发布设计
本仓提供Goldilocks批量求逆和逐元素批量除法，16交错扫描上下文、最大批长65536，最多两个任务在途但输入批次不可交错。零分母对应结果0和zero标记，并以ZERO_DENOMINATOR完成，不伪装成普通成功。空批、参数错误和帧错误行为独立；16上下文不是16条外部请求lane。
工程证据与集成
项目介绍 · 原生接口 · 复现步骤 · 性能条件 · 综合范围 · 许可
支持配置、数学模型、测试场景、性能条件和综合结论分别以对应文档为准。仿真、综合与板级或硅后实测应区分理解，不能把某一配置的验证结论推广到全部参数或目标。这是独立计算模块，不是端到端零知识证明生成系统。
定制集成与开源许可
如需可选的 ASIC/FPGA 加速器定制开发与集成，请到 OpenRTL Lab 官方网站了解服务与联系方式。MIT 许可代码可免费用于商业用途，保留适用的版权、许可和第三方声明；付费定制与支持是独立、可选的服务。
发布下载
以上下载提供本版本硬件源码与随包 RTL。源码包与在线源码树的注释及文档可能不同；集成使用产品文件清单，验证范围以链接文档为准。