AXI-Lite PWM Controller

This project implements a PWM (Pulse Width Modulation) generator with an AXI-Lite slave interface for control.

Modules

pwm.v: A simple PWM generator module.
axi_pwm.sv: An AXI-Lite slave wrapper for the PWM module. It exposes control and data registers to an AXI bus.

The AXI-Lite interface provides access to the following registers:

0x0 (ADDR_CONTROL): Control register
- [0]: enable (1 to enable PWM, 0 to disable)
- [1]: soft_reset (write 1 to reset the PWM core)
0x4 (ADDR_PERIOD): Sets the PWM period.
0x8 (ADDR_DUTY): Sets the PWM duty cycle.

The project includes files for synthesis and simulation:

synth_*.ys: Yosys synthesis scripts for different targets (Xilinx FPGA, Skywater 130nm).
tb_*.sv: SystemVerilog testbenches for the PWM and AXI-PWM modules.
wave.do: Waveform script for simulation visualization.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Code_files		Code_files
libs		libs
out		out
reports		reports
work		work
.history_sta		.history_sta
README.md		README.md
axi_pwm.sv		axi_pwm.sv
axi_pwm.vcd		axi_pwm.vcd
axi_pwm_day1.cr.mti		axi_pwm_day1.cr.mti
axi_pwm_day1.mpf		axi_pwm_day1.mpf
axi_pwm_sky130.dot		axi_pwm_sky130.dot
axi_pwm_sky130.png		axi_pwm_sky130.png
axi_pwm_synth.json		axi_pwm_synth.json
axi_pwm_synth.v		axi_pwm_synth.v
axi_pwm_xilinx.v		axi_pwm_xilinx.v
constraints.sdc		constraints.sdc
hello		hello
hello_test.v		hello_test.v
pwm.gtkw		pwm.gtkw
pwm.v		pwm.v
pwm.vcd		pwm.vcd
pwm_sky130.dot		pwm_sky130.dot
pwm_sky130.png		pwm_sky130.png
sim_pwm		sim_pwm
sta_sky130.tcl		sta_sky130.tcl
synth_axi_pwm.ys		synth_axi_pwm.ys
synth_fpga.ys		synth_fpga.ys
synth_sky130.ys		synth_sky130.ys
tb_axi_pwm.sv		tb_axi_pwm.sv
tb_pwm.sv		tb_pwm.sv
tb_pwm_icarus.sv		tb_pwm_icarus.sv
test.vcd		test.vcd
transcript		transcript
vsim.wlf		vsim.wlf
wave.do		wave.do