[amd-spirv-backend][Backend] Identify and address translator/backend delta

[lamb-j]

Once optional support for the SPIRV backend is added for --offload-arch=amdgcnspirv, we need to identify the delta between that and the existing default SPIRV-translator-based implementation.

Likely differences may include:

• relaxing casts
• carrying specific attributes as non-semantic metadata
• incorporating debug information
• etc

We can assess the delta with some initial testing of:

• Directly compare output of translator and backend (and try reverse translating both)
• LLVM LIT spirv-related tests
• Comgr tests

Sub/child/dependent issues can be created as issues are identified. When possible, fixes should land in upstream llvm-project, otherwise they should land in ROCm/llvm-project.

[jmmartinez]

The first issue we encountered with @mgcarrasco is that with -fembed-bitcode-marker, the llvm-ir contains a [0 x i8] array; which is illegal in kernel code in spirv.

I decided to keep the global, but extend it as a [1 x i8] zeroinitialized array.

• pre-commit fembed-bitcode=marker
• -fembed-bitcode=marker implementation

An alternative could have been to drop the global (I don't think the bitcode marker makes sense in this backend). Another alternative could have been to add an option -fembed-bitcode-cmdline-only and avoid the bitcode global.