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@brbrr brbrr commented Sep 10, 2025

The current implementation fails to init_compile SysClkOutput. The problem is with calculating DIVN1. For STM32H750IB chips, DIVN1 has only 2 parents, and PLLFRACN is a source type.

        const DIVM1val = ClockNodeTypes{
            .div = .{},
        };

        const PLLFRACNval = ClockNodeTypes{
            .source = .{},
        };

        const DIVN1val = ClockNodeTypes{
            .mulfrac = .{},
        };
        const DIVN1: ClockNode = .{
            .name = "DIVN1",
            .Nodetype = DIVN1val,
            .parents = &[_]*const ClockNode{ &DIVM1, &PLLFRACN },
        };

@RecursiveError
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I'll merge this change for now, while I figure out whether .frac is actually a useful type or not (to be honest I don't even remember why it exists)

@RecursiveError RecursiveError merged commit a574bdd into RecursiveError:main Sep 11, 2025
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2 participants