Verilog UART Tx Readme

Introduction

This is a basic UART to AXI Stream IP core, written in Verilog with testbench.

The AXI4-Stream UART Transmitter (uart_tx) is designed to serialize parallel data received via an AXI4-Stream interface into standard UART format. It manages start, data, and stop bit framing and ensures proper baud-rate timing using a programmable prescaler.

The module provides AXI4-Stream handshaking (tvalid, tready) for reliable data transfer, generates the serial transmit signal (txd), and indicates operational status through the busy flag. Operation is synchronous to the input clock with one-cycle control latency.

Transmission Overview

The UART transmitter logic follows these steps:

1. Idle State

   • txd remains high (1) when no data is being transmitted.
   • s_axis_tready is asserted (1) to indicate readiness for new data.

2. Data Acceptance

   • When s_axis_tvalid and s_axis_tready are both high, input data (s_axis_tdata) is latched.
   • A start bit (0) is output, busy is asserted (1), and the internal prescaler begins counting baud intervals.

3. Data Transmission

   • Each bit of s_axis_tdata is shifted out, least significant bit (LSB) first.
   • The prescale value determines the duration of each bit interval (bit_time = prescale × 8 cycles).

4. Stop Bit

   • After all data bits, a stop bit (1) is transmitted.
   • Once the stop bit completes, busy is deasserted (0), and the module returns to idle.

5. Backpressure Handling

   • While transmitting, s_axis_tready is held low to prevent new data acceptance until the ongoing frame completes.

Source Files

rtl/uart.v     : Wrapper for complete UART
rtl/uart_rx.v  : UART receiver implementation
rtl/spec_to_rtl_uart_tx.v  : UART transmitter implementation

tb/new_uart_tx_tb.sv : Testbench to test modified uart_tx.sv

Testing

Steps to compile and run the test -

Setup to run -

- Synth run
    - check correct filelist (rtl files provided) in /code/scripts/synth.tcl
    - check -top correctly mentioned
    - to run synth -
        - Run  "docker-compose run synth"
        - check log in /code/rundir/synth.log (fix Errors/Warnings in logs)

- Simulation run
    - to run simulation -
        - Run "docker-compose run verif"
        - check log in /code/rundir/a.out