Kernel: Set up initial exception stack when going into EL1 on aarch64

When an exception is triggered on aarch64, the processor always switches
to the exception stack which is defined by the SP_EL1 register.

Author: FireFox317

Kernel/Arch/aarch64/ASM_wrapper.h

@@ -23,6 +23,11 @@ inline void set_ttbr0_el1(FlatPtr ttbr0_el1)
     asm("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
 }
 
+inline void set_sp_el1(FlatPtr sp_el1)
+{
+    asm("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
+}
+
 inline void flush()
 {
     asm("dsb ish");

Kernel/Arch/aarch64/Exceptions.cpp

@@ -46,6 +46,10 @@ static void drop_to_el1()
     hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
     Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
 
+    // Set up initial exception stack
+    // FIXME: Define in linker script
+    Aarch64::Asm::set_sp_el1(0x40000);
+
     Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
 
     // Mask (disable) all interrupts