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Kernel: Support all Intel-defined extended CPUID feature flags for EAX=7
We're now able to detect all the extended CPUID feature flags from EBX/ECX/EDX for EAX=7 :^)
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3 files changed

+405
-12
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‎Kernel/Arch/x86/CPUID.h‎

Lines changed: 97 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ class CPUID {
3737
u32 m_edx { 0xffffffff };
3838
};
3939

40-
AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
40+
AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
4141
/* EAX=1, ECX */ //
4242
SSE3 = CPUFeature(1u) << 0u, // Streaming SIMD Extensions 3
4343
PCLMULQDQ = CPUFeature(1u) << 1u, // PCLMULDQ Instruction
@@ -105,20 +105,105 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
105105
IA64 = CPUFeature(1u) << 62u, // IA64 processor emulating x86
106106
PBE = CPUFeature(1u) << 63u, // Pending Break Enable
107107
/* EAX=7, EBX */ //
108-
SMEP = CPUFeature(1u) << 64u, // Supervisor Mode Execution Protection
109-
RDSEED = CPUFeature(1u) << 65u, // RDSEED Instruction
110-
SMAP = CPUFeature(1u) << 66u, // Supervisor Mode Access Prevention
108+
FSGSBASE = CPUFeature(1u) << 64u, // Access to base of %fs and %gs
109+
TSC_ADJUST = CPUFeature(1u) << 65u, // IA32_TSC_ADJUST MSR
110+
SGX = CPUFeature(1u) << 66u, // Software Guard Extensions
111+
BMI1 = CPUFeature(1u) << 67u, // Bit Manipulation Instruction Set 1
112+
HLE = CPUFeature(1u) << 68u, // TSX Hardware Lock Elision
113+
AVX2 = CPUFeature(1u) << 69u, // Advanced Vector Extensions 2
114+
FDP_EXCPTN_ONLY = CPUFeature(1u) << 70u, // FDP_EXCPTN_ONLY
115+
SMEP = CPUFeature(1u) << 71u, // Supervisor Mode Execution Protection
116+
BMI2 = CPUFeature(1u) << 72u, // Bit Manipulation Instruction Set 2
117+
ERMS = CPUFeature(1u) << 73u, // Enhanced REP MOVSB/STOSB
118+
INVPCID = CPUFeature(1u) << 74u, // INVPCID Instruction
119+
RTM = CPUFeature(1u) << 75u, // TSX Restricted Transactional Memory
120+
PQM = CPUFeature(1u) << 76u, // Platform Quality of Service Monitoring
121+
ZERO_FCS_FDS = CPUFeature(1u) << 77u, // FPU CS and FPU DS deprecated
122+
MPX = CPUFeature(1u) << 78u, // Intel MPX (Memory Protection Extensions)
123+
PQE = CPUFeature(1u) << 79u, // Platform Quality of Service Enforcement
124+
AVX512_F = CPUFeature(1u) << 80u, // AVX-512 Foundation
125+
AVX512_DQ = CPUFeature(1u) << 81u, // AVX-512 Doubleword and Quadword Instructions
126+
RDSEED = CPUFeature(1u) << 82u, // RDSEED Instruction
127+
ADX = CPUFeature(1u) << 83u, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
128+
SMAP = CPUFeature(1u) << 84u, // Supervisor Mode Access Prevention
129+
AVX512_IFMA = CPUFeature(1u) << 85u, // AVX-512 Integer Fused Multiply-Add Instructions
130+
PCOMMIT = CPUFeature(1u) << 86u, // PCOMMIT Instruction
131+
CLFLUSHOPT = CPUFeature(1u) << 87u, // CLFLUSHOPT Instruction
132+
CLWB = CPUFeature(1u) << 88u, // CLWB Instruction
133+
INTEL_PT = CPUFeature(1u) << 89u, // Intel Processor Tracing
134+
AVX512_PF = CPUFeature(1u) << 90u, // AVX-512 Prefetch Instructions
135+
AVX512_ER = CPUFeature(1u) << 91u, // AVX-512 Exponential and Reciprocal Instructions
136+
AVX512_CD = CPUFeature(1u) << 92u, // AVX-512 Conflict Detection Instructions
137+
SHA = CPUFeature(1u) << 93u, // Intel SHA Extensions
138+
AVX512_BW = CPUFeature(1u) << 94u, // AVX-512 Byte and Word Instructions
139+
AVX512_VL = CPUFeature(1u) << 95u, // AVX-512 Vector Length Extensions
111140
/* EAX=7, ECX */ //
112-
UMIP = CPUFeature(1u) << 67u, // User-Mode Instruction Prevention
141+
PREFETCHWT1 = CPUFeature(1u) << 96u, // PREFETCHWT1 Instruction
142+
AVX512_VBMI = CPUFeature(1u) << 97u, // AVX-512 Vector Bit Manipulation Instructions
143+
UMIP = CPUFeature(1u) << 98u, // UMIP
144+
PKU = CPUFeature(1u) << 99u, // Memory Protection Keys for User-mode pages
145+
OSPKU = CPUFeature(1u) << 100u, // PKU enabled by OS
146+
WAITPKG = CPUFeature(1u) << 101u, // Timed pause and user-level monitor/wait
147+
AVX512_VBMI2 = CPUFeature(1u) << 102u, // AVX-512 Vector Bit Manipulation Instructions 2
148+
CET_SS = CPUFeature(1u) << 103u, // Control Flow Enforcement (CET) Shadow Stack
149+
GFNI = CPUFeature(1u) << 104u, // Galois Field Instructions
150+
VAES = CPUFeature(1u) << 105u, // Vector AES instruction set (VEX-256/EVEX)
151+
VPCLMULQDQ = CPUFeature(1u) << 106u, // CLMUL instruction set (VEX-256/EVEX)
152+
AVX512_VNNI = CPUFeature(1u) << 107u, // AVX-512 Vector Neural Network Instructions
153+
AVX512_BITALG = CPUFeature(1u) << 108u, // AVX-512 BITALG Instructions
154+
TME_EN = CPUFeature(1u) << 109u, // IA32_TME related MSRs are supported
155+
AVX512_VPOPCNTDQ = CPUFeature(1u) << 110u, // AVX-512 Vector Population Count Double and Quad-word
156+
/* ECX Bit 15 */ // Reserved
157+
INTEL_5_LEVEL_PAGING = CPUFeature(1u) << 112u, // Intel 5-Level Paging
158+
RDPID = CPUFeature(1u) << 113u, // RDPID Instruction
159+
KL = CPUFeature(1u) << 114u, // Key Locker
160+
/* ECX Bit 24 */ // Reserved
161+
CLDEMOTE = CPUFeature(1u) << 116u, // Cache Line Demote
162+
/* ECX Bit 26 */ // Reserved
163+
MOVDIRI = CPUFeature(1u) << 118u, // MOVDIRI Instruction
164+
MOVDIR64B = CPUFeature(1u) << 119u, // MOVDIR64B Instruction
165+
ENQCMD = CPUFeature(1u) << 120u, // ENQCMD Instruction
166+
SGX_LC = CPUFeature(1u) << 121u, // SGX Launch Configuration
167+
PKS = CPUFeature(1u) << 122u, // Protection Keys for Supervisor-Mode Pages
168+
/* EAX=7, EDX */ //
169+
/* ECX Bit 0-1 */ // Reserved
170+
AVX512_4VNNIW = CPUFeature(1u) << 125u, // AVX-512 4-register Neural Network Instructions
171+
AVX512_4FMAPS = CPUFeature(1u) << 126u, // AVX-512 4-register Multiply Accumulation Single precision
172+
FSRM = CPUFeature(1u) << 127u, // Fast Short REP MOVSB
173+
/* ECX Bit 5-7 */ // Reserved
174+
AVX512_VP2INTERSECT = CPUFeature(1u) << 131u, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
175+
SRBDS_CTRL = CPUFeature(1u) << 132u, // Special Register Buffer Data Sampling Mitigations
176+
MD_CLEAR = CPUFeature(1u) << 133u, // VERW instruction clears CPU buffers
177+
RTM_ALWAYS_ABORT = CPUFeature(1u) << 134u, // All TSX transactions are aborted
178+
/* ECX Bit 12 */ // Reserved
179+
TSX_FORCE_ABORT = CPUFeature(1u) << 136u, // TSX_FORCE_ABORT MSR
180+
SERIALIZE = CPUFeature(1u) << 137u, // Serialize instruction execution
181+
HYBRID = CPUFeature(1u) << 138u, // Mixture of CPU types in processor topology
182+
TSXLDTRK = CPUFeature(1u) << 139u, // TSX suspend load address tracking
183+
/* ECX Bit 17 */ // Reserved
184+
PCONFIG = CPUFeature(1u) << 141u, // Platform configuration (Memory Encryption Technologies Instructions)
185+
LBR = CPUFeature(1u) << 142u, // Architectural Last Branch Records
186+
CET_IBT = CPUFeature(1u) << 143u, // Control flow enforcement (CET) indirect branch tracking
187+
/* ECX Bit 21 */ // Reserved
188+
AMX_BF16 = CPUFeature(1u) << 145u, // Tile computation on bfloat16 numbers
189+
AVX512_FP16 = CPUFeature(1u) << 146u, // AVX512-FP16 half-precision floating-point instructions
190+
AMX_TILE = CPUFeature(1u) << 147u, // Tile architecture
191+
AMX_INT8 = CPUFeature(1u) << 148u, // Tile computation on 8-bit integers
192+
SPEC_CTRL = CPUFeature(1u) << 149u, // Speculation Control
193+
STIBP = CPUFeature(1u) << 150u, // Single Thread Indirect Branch Predictor
194+
L1D_FLUSH = CPUFeature(1u) << 151u, // IA32_FLUSH_CMD MSR
195+
IA32_ARCH_CAPABILITIES = CPUFeature(1u) << 152u, // IA32_ARCH_CAPABILITIES MSR
196+
IA32_CORE_CAPABILITIES = CPUFeature(1u) << 153u, // IA32_CORE_CAPABILITIES MSR
197+
SSBD = CPUFeature(1u) << 154u, // Speculative Store Bypass Disable
113198
/* EAX=80000001h, EDX */ //
114-
SYSCALL = CPUFeature(1u) << 68u, // SYSCALL/SYSRET Instructions
115-
NX = CPUFeature(1u) << 69u, // NX bit
116-
RDTSCP = CPUFeature(1u) << 70u, // RDTSCP Instruction
117-
LM = CPUFeature(1u) << 71u, // Long Mode
199+
SYSCALL = CPUFeature(1u) << 155u, // SYSCALL/SYSRET Instructions
200+
NX = CPUFeature(1u) << 156u, // NX bit
201+
RDTSCP = CPUFeature(1u) << 157u, // RDTSCP Instruction
202+
LM = CPUFeature(1u) << 158u, // Long Mode
118203
/* EAX=80000007h, EDX */ //
119-
CONSTANT_TSC = CPUFeature(1u) << 72u, // Invariant TSC
120-
NONSTOP_TSC = CPUFeature(1u) << 73u, // Invariant TSC
121-
__End = CPUFeature(1u) << 127u);
204+
CONSTANT_TSC = CPUFeature(1u) << 159u, // Invariant TSC
205+
NONSTOP_TSC = CPUFeature(1u) << 160u, // Invariant TSC
206+
__End = CPUFeature(1u) << 255u);
122207

123208
StringView cpu_feature_to_string_view(CPUFeature::Type const&);
124209

‎Kernel/Arch/x86/common/CPUID.cpp‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,14 +134,167 @@ StringView cpu_feature_to_string_view(CPUFeature::Type const& feature)
134134
return "ia64"sv;
135135
if (feature == CPUFeature::PBE)
136136
return "pbe"sv;
137+
if (feature == CPUFeature::FSGSBASE)
138+
return "fsgsbase"sv;
139+
if (feature == CPUFeature::TSC_ADJUST)
140+
return "tsc_adjust"sv;
141+
if (feature == CPUFeature::SGX)
142+
return "sgx"sv;
143+
if (feature == CPUFeature::BMI1)
144+
return "bmi1"sv;
145+
if (feature == CPUFeature::HLE)
146+
return "hle"sv;
147+
if (feature == CPUFeature::AVX2)
148+
return "avx2"sv;
149+
if (feature == CPUFeature::FDP_EXCPTN_ONLY)
150+
return "fdp_excptn_only"sv;
137151
if (feature == CPUFeature::SMEP)
138152
return "smep"sv;
153+
if (feature == CPUFeature::BMI2)
154+
return "bmi2"sv;
155+
if (feature == CPUFeature::ERMS)
156+
return "erms"sv;
157+
if (feature == CPUFeature::INVPCID)
158+
return "invpcid"sv;
159+
if (feature == CPUFeature::RTM)
160+
return "rtm"sv;
161+
if (feature == CPUFeature::PQM)
162+
return "pqm"sv;
163+
if (feature == CPUFeature::ZERO_FCS_FDS)
164+
return "zero_fcs_fds"sv;
165+
if (feature == CPUFeature::MPX)
166+
return "mpx"sv;
167+
if (feature == CPUFeature::PQE)
168+
return "pqe"sv;
169+
if (feature == CPUFeature::AVX512_F)
170+
return "avx512_f"sv;
171+
if (feature == CPUFeature::AVX512_DQ)
172+
return "avx512_dq"sv;
139173
if (feature == CPUFeature::RDSEED)
140174
return "rdseed"sv;
175+
if (feature == CPUFeature::ADX)
176+
return "adx"sv;
141177
if (feature == CPUFeature::SMAP)
142178
return "smap"sv;
179+
if (feature == CPUFeature::AVX512_IFMA)
180+
return "avx512_ifma"sv;
181+
if (feature == CPUFeature::PCOMMIT)
182+
return "pcommit"sv;
183+
if (feature == CPUFeature::CLFLUSHOPT)
184+
return "clflushopt"sv;
185+
if (feature == CPUFeature::CLWB)
186+
return "clwb"sv;
187+
if (feature == CPUFeature::INTEL_PT)
188+
return "intel_pt"sv;
189+
if (feature == CPUFeature::AVX512_PF)
190+
return "avx512_pf"sv;
191+
if (feature == CPUFeature::AVX512_ER)
192+
return "avx512_er"sv;
193+
if (feature == CPUFeature::AVX512_CD)
194+
return "avx512_cd"sv;
195+
if (feature == CPUFeature::SHA)
196+
return "sha"sv;
197+
if (feature == CPUFeature::AVX512_BW)
198+
return "avx512_bw"sv;
199+
if (feature == CPUFeature::AVX512_VL)
200+
return "avx512_vl"sv;
201+
if (feature == CPUFeature::PREFETCHWT1)
202+
return "prefetchwt1"sv;
203+
if (feature == CPUFeature::AVX512_VBMI)
204+
return "avx512_vbmi"sv;
143205
if (feature == CPUFeature::UMIP)
144206
return "umip"sv;
207+
if (feature == CPUFeature::PKU)
208+
return "pku"sv;
209+
if (feature == CPUFeature::OSPKU)
210+
return "ospku"sv;
211+
if (feature == CPUFeature::WAITPKG)
212+
return "waitpkg"sv;
213+
if (feature == CPUFeature::AVX512_VBMI2)
214+
return "avx512_vbmi2"sv;
215+
if (feature == CPUFeature::CET_SS)
216+
return "cet_ss"sv;
217+
if (feature == CPUFeature::GFNI)
218+
return "gfni"sv;
219+
if (feature == CPUFeature::VAES)
220+
return "vaes"sv;
221+
if (feature == CPUFeature::VPCLMULQDQ)
222+
return "vpclmulqdq"sv;
223+
if (feature == CPUFeature::AVX512_VNNI)
224+
return "avx512_vnni"sv;
225+
if (feature == CPUFeature::AVX512_BITALG)
226+
return "avx512_bitalg"sv;
227+
if (feature == CPUFeature::TME_EN)
228+
return "tme_en"sv;
229+
if (feature == CPUFeature::AVX512_VPOPCNTDQ)
230+
return "avx512_vpopcntdq"sv;
231+
if (feature == CPUFeature::INTEL_5_LEVEL_PAGING)
232+
return "intel_5_level_paging"sv;
233+
if (feature == CPUFeature::RDPID)
234+
return "rdpid"sv;
235+
if (feature == CPUFeature::KL)
236+
return "kl"sv;
237+
if (feature == CPUFeature::CLDEMOTE)
238+
return "cldemote"sv;
239+
if (feature == CPUFeature::MOVDIRI)
240+
return "movdiri"sv;
241+
if (feature == CPUFeature::MOVDIR64B)
242+
return "movdir64b"sv;
243+
if (feature == CPUFeature::ENQCMD)
244+
return "enqcmd"sv;
245+
if (feature == CPUFeature::SGX_LC)
246+
return "sgx_lc"sv;
247+
if (feature == CPUFeature::PKS)
248+
return "pks"sv;
249+
if (feature == CPUFeature::AVX512_4VNNIW)
250+
return "avx512_4vnniw"sv;
251+
if (feature == CPUFeature::AVX512_4FMAPS)
252+
return "avx512_4fmaps"sv;
253+
if (feature == CPUFeature::FSRM)
254+
return "fsrm"sv;
255+
if (feature == CPUFeature::AVX512_VP2INTERSECT)
256+
return "avx512_vp2intersect"sv;
257+
if (feature == CPUFeature::SRBDS_CTRL)
258+
return "srbds_ctrl"sv;
259+
if (feature == CPUFeature::MD_CLEAR)
260+
return "md_clear"sv;
261+
if (feature == CPUFeature::RTM_ALWAYS_ABORT)
262+
return "rtm_always_abort"sv;
263+
if (feature == CPUFeature::TSX_FORCE_ABORT)
264+
return "tsx_force_abort"sv;
265+
if (feature == CPUFeature::SERIALIZE)
266+
return "serialize"sv;
267+
if (feature == CPUFeature::HYBRID)
268+
return "hybrid"sv;
269+
if (feature == CPUFeature::TSXLDTRK)
270+
return "tsxldtrk"sv;
271+
if (feature == CPUFeature::PCONFIG)
272+
return "pconfig"sv;
273+
if (feature == CPUFeature::LBR)
274+
return "lbr"sv;
275+
if (feature == CPUFeature::CET_IBT)
276+
return "cet_ibt"sv;
277+
if (feature == CPUFeature::AMX_BF16)
278+
return "amx_bf16"sv;
279+
if (feature == CPUFeature::AVX512_FP16)
280+
return "avx512_fp16"sv;
281+
if (feature == CPUFeature::AMX_TILE)
282+
return "amx_tile"sv;
283+
if (feature == CPUFeature::AMX_INT8)
284+
return "amx_int8"sv;
285+
if (feature == CPUFeature::SPEC_CTRL)
286+
return "spec_ctrl"sv;
287+
if (feature == CPUFeature::STIBP)
288+
return "stibp"sv;
289+
// NOTE: This is called flush_l1d on Linux, but L1D_FLUSH in the Intel manual.
290+
if (feature == CPUFeature::L1D_FLUSH)
291+
return "l1d_flush"sv;
292+
if (feature == CPUFeature::IA32_ARCH_CAPABILITIES)
293+
return "ia32_arch_capabilities"sv;
294+
if (feature == CPUFeature::IA32_CORE_CAPABILITIES)
295+
return "ia32_code_capabilities"sv;
296+
if (feature == CPUFeature::SSBD)
297+
return "ssbd"sv;
145298
if (feature == CPUFeature::SYSCALL)
146299
return "syscall"sv;
147300
if (feature == CPUFeature::NX)

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