⚡Nanoprocessor Design⚡

Top Level Component Timing Diagrams ⏩

Testing Final Design on Basys3 Board ⏩

Top Level Component Interface ⏩

-- Top Level Component Interface
COMPONENT Nanoprocessor_Design
     Port ( Clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         Register7 : out STD_LOGIC_VECTOR (3 downto 0);
         OverflowFlag : out STD_LOGIC;
         ZeroFlag : out STD_LOGIC;
         To7Segment : out STD_LOGIC_VECTOR (6 downto 0);
         Display : out STD_LOGIC_VECTOR (3 downto 0));
end COMPONENT;  

➡Bitstream file (.bit format) is located at ❝Nanoprocessor_Design.runs/impl_2/Nanoprocessor_Design.bit❞ ✨✨