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Implementation of the MIPS architecture in VHDL using Xilinx ISE 14.7 on the Spartan-3E board. Reference Website: https://www.d.umn.edu/~gshute/mips/MIPS.html; https://www.cise.ufl.edu/~mssz/CompOrg/CDA-proc.html

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MIPS-32

MIPS (Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

Image of MIPS architecture

Components

Combinational

  • MUX
  • Sign - Extender
  • Adder
  • ALU
  • ALU Control
  • PC updte Control
  • Register File

State

  • Program Counter
  • Register
  • Program Memory
  • Data Memory

ALU

Reference

Function ALU Control Semantics
AND 0000 F = A and B (bitwise AND); Z update, V,C = zero
OR 0001 F = A or B (bitwise OR); Z update, V,C = zero
add 0010 F = A + B; Z,V,C update
sub 0110 F = A - B; Z,V,C update
slt 0111 F = (A < B) ? 1 : 0
NOR 1100 F = ~ ( A or B ) (bitwise NOR); Z update, V,C = zero

Register

Reference

Register Number Conventional Name Usage
$0 $zero Hard-wired to 0
$1 $at Reserved for pseudo-instructions
$2 - $3 $v0, $v1 Return values from functions
$4 - $7 $a0 - $a3 Arguments to functions - not preserved by subprograms
$8 - $15 $t0 - $t7 Temporary data, not preserved by subprograms
$16 - $23 $s0 - $s7 Saved registers, preserved by subprograms
$24 - $25 $t8 - $t9 More temporary registers, not preserved by subprograms
$26 - $27 $k0 - $k1 Reserved for kernel. Do not use.
$28 $gp Global Area Pointer (base of global data segment)
$29 $sp Stack Pointer
$30 $fp Frame Pointer
$31 $ra Return Address

ALU Control

Reference

Image of MIPS ALU Control

About

Implementation of the MIPS architecture in VHDL using Xilinx ISE 14.7 on the Spartan-3E board. Reference Website: https://www.d.umn.edu/~gshute/mips/MIPS.html; https://www.cise.ufl.edu/~mssz/CompOrg/CDA-proc.html

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