Upstream sync #73
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Upstream sync #73
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kernel: share a single CellTypes within a pass
The only user of this API right now is the puzzle3d benchmark and it sees a slight reduction in CNF size from this, but the performance difference is within the noise of measurement on my system. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Using LFSR counter for ezSAT::manyhot()
Add info-file and cover features to write_btor
Improve write_btor symbol handling
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
kernel: speedup by using more pass-by-const-ref
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
This reverts commit 7b2a85a.
deminout: prevent any constant assignment from demoting to input
Adding error message for when size (width) of number literal is zero
This makes adding more FF types in the future much more manageable. Fixes YosysHQ#1824.
IdString: use more ID::*, make them easier to use, speed up IdString::in()
ast: cap dynamic range select to size of signal, suppresses warnings
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
* If there is an explicit inference attribute set on a $mem cell,
e.g. (* ram_block *), then it is arguably incorrect to map such
a memory to $dff/$mux cells.
* If memory_map tries to lower a memory that was intended to
be mapped to a large BRAM, it often takes extraordinarily long
time to finish, produces an extremely large log file, and outputs
an unusable design.
After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
cxxrtl: minor documentation and usability improvements
And make {get,set}_src_attribute use those functions.
select: add select -unset option
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
Clean up `passes/cmds/scatter.cc`.
Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
Verilog frontend: add location information to parsed constants
Signed-off-by: David Shah <dave@ds0.me>
rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute
qbfsat: Fix illegal use of 'stdout' identifier
[pull] master from YosysHQ:master
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
…isable_ramb18e_w2' into upstream_sync
This is an Octopus Merge commit of the following branches: wip/carry4-cout wip/disable-primitives wip/disable_ramb18e_w2 Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Closing, superseded by #74 |
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Yosys upstream sync.
There is a fix for the ABC issue described here, that switches the w/b value in the abc9_xc7.box techlib