Welcome to my documentation of the RISC-V SoC Tapeout Program by VSD
This repository gives the overview of my weekly tasks through this Journey, with each week maintained in a new and unique GitHub repository and the overall progress will be shared here.
"Right from Market analysis, spec to GDSII, we design and manufacture silicon step by step, that too while mastering open-source tools and taking part in India's Semiconductor Mission through a great opportunity given by VSD team and most importantly learning the indusrtial flow as an engineer."
Every week's work is given as each repo
| Week | Focus Area | Repository Link | Status |
|---|---|---|---|
| Week 0 | 🔧 Environment Setup & Tool Installation | Week0 | ✅ Done |
| Week 1 | 📝 RTL Design Basics | (Coming Soon) | ⏳ Pending |
| Week 2 | 🔄 RTL to Gate-Level Synthesis | (Upcoming) | ⏳ Pending |
| Week 3 | 🏗️ Floorplanning & Placement | (Upcoming) | ⏳ Pending |
| Week 4 | ⏰ Clock Tree & Routing | (Upcoming) | ⏳ Pending |
| Week 5+ | 🎯 Tapeout Prep & Verification | (Upcoming) | ⏳ Pending |
📌 Focus: Installing and verifying the open-source EDA toolchain on Ubuntu 22.04
| Tool | Purpose | Status |
|---|---|---|
| Yosys | RTL Synthesis | ✅ Installed |
| Icarus Verilog | Simulation & Testbench | ✅ Installed |
| GTKWave | Waveform Viewer | ✅ Installed |
| Ngspice | Circuit Simulation | ✅ Installed |
| Magic | Layout & DRC | ✅ Installed |
| OpenLane | Complete RTL → GDSII Flow | ✅ Installed |
- Set up the EDA toolchain successfully on Ubuntu 22.04.
- Understood the importance of each tool in the RTL-to-GDSII flow.
- Launch Pad is ready for Week 1 RTL design tasks.
I am grateful to:
- Kunal Ghosh and the VSD team
- RISC-V International and Efabless
- The open-source EDA community for enabling this initiative
- Start Week 1: RTL Design Basics
- Document progress in a new repo
- Continue building toward full SoC tapeout
👨💻 Maintainer: Tatikonda Ramakrishna